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| author | n8tlarsen <96437952+n8tlarsen@users.noreply.github.com> | 2022-12-19 17:45:53 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-19 17:45:53 -0600 |
| commit | c8d60d2910137381c9e6101b92976d47e256701e (patch) | |
| tree | 7a17dfd1d353a20b982df9c0b4211be070742dd6 /book/en | |
| parent | f52b5fd1c4410e972ec642e331a86850c9a75ef2 (diff) | |
Improve basepri explanation
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
Diffstat (limited to 'book/en')
| -rw-r--r-- | book/en/src/internals/targets.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/book/en/src/internals/targets.md b/book/en/src/internals/targets.md index 0104cdb..65c0712 100644 --- a/book/en/src/internals/targets.md +++ b/book/en/src/internals/targets.md @@ -1,7 +1,7 @@ # Target Architecture While RTIC can currently target all Cortex-m devices there are some key architecure differences that -users should be aware. Namely the absence of hardware priority ceiling (BASEPRI) support in the +users should be aware of. Namely the absence of Base Priority Mask Register (`BASEPRI`) which lends itself exceptionally well to the hardware priority ceiling support used in RTIC, in the ARMv6-M and ARMv8-M-base architectures requires a few tweaks from RTIC to deliver the same features. These differences result in two flavors of critical sections: priority ceiling, and source masking. Table 1 below shows a list of Cortex-m processors and which type of critical section they |