diff options
| author | n8tlarsen <96437952+n8tlarsen@users.noreply.github.com> | 2022-12-19 18:16:25 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-19 18:16:25 -0600 |
| commit | 70ebcc409ff4e34764337a978882a25f34484c4f (patch) | |
| tree | 86c4d43ac6e5552f40fe8a6aa691ea6d21a15b4c /book | |
| parent | 60132495d96f99af525df0122989f08b5206e854 (diff) | |
Clarify BASEPRI and NVIC interaction
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
Diffstat (limited to 'book')
| -rw-r--r-- | book/en/src/internals/targets.md | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/book/en/src/internals/targets.md b/book/en/src/internals/targets.md index bdfb24b..606191d 100644 --- a/book/en/src/internals/targets.md +++ b/book/en/src/internals/targets.md @@ -28,8 +28,10 @@ This implementation is covered in depth by Chapter 4.5 of this book. ## Source Masking -Since there is no hardware support for a priority ceiling, RTIC must instead rely on the Nested -Vectored Interrupt Controller (NVIC) present in the core architecture. Consider Figure 1 below, +Without a `BASEPRI` register which allows for directly setting a priority ceiling in the Nested +Vectored Interrupt Controller (NVIC), RTIC must instead rely on disabling (masking) interrupts. + +Consider Figure 1 below, showing two tasks A and B where A has higher priority but shares a resource with B. #### *Figure 1: Shared Resources and Source Masking* |