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| author | Román Cárdenas Rodríguez <rcardenas.rod@gmail.com> | 2024-03-20 21:06:47 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-20 20:06:47 +0000 |
| commit | 4060c3def88f82d4e4f48de7137ce365167ef265 (patch) | |
| tree | f326f0687092cab2b772952b579d63d12d3d34aa /rtic-macros/Cargo.toml | |
| parent | 22ac33a826dedacde5d3d5c0964ff072555a9b32 (diff) | |
RISC-V support over CLINT (#815)
* Rebase to master
* using interrupt_mod
* bug fixes
* fix other backends
* Add changelog
* forgot about rtic-macros
* backend-specific configuration
* core peripherals optional over macro argument
* pre_init_preprocessing binding
* CI for RISC-V (WIP)
* separation of concerns
* add targets for RISC-V examples
* remove qemu feature
* prepare examples folder
* move examples all together
* move ci out of examples
* minor changes
* add cortex-m
* new xtask: proof of concept
* fix build.yml
* feature typo
* clean rtic examples
* reproduce weird issue
* remove unsafe code in user app
* update dependencies
* allow builds on riscv32imc
* let's fix QEMU
* Update .github/workflows/build.yml
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* New build.rs
* removing test features
* adapt ui test to new version of clippy
* add more examples to RISC-V backend
* proper configuration of heapless for riscv32imc
* opt-out examples for riscv32imc
* point to new version of riscv-slic
* adapt new macro bindings
* adapt examples and CI to stable
* fix cortex-m CI
* Review
---------
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
Diffstat (limited to 'rtic-macros/Cargo.toml')
| -rw-r--r-- | rtic-macros/Cargo.toml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/rtic-macros/Cargo.toml b/rtic-macros/Cargo.toml index 423fe31..443ed0d 100644 --- a/rtic-macros/Cargo.toml +++ b/rtic-macros/Cargo.toml @@ -36,8 +36,8 @@ cortex-m-basepri = [] riscv-esp32c3 = [] # riscv-clic = [] # riscv-ch32 = [] - - +riscv-slic = [] + # backend API test test-template = [] |