RISC-V support over CLINT (#815)

* Rebase to master

* using interrupt_mod

* bug fixes

* fix other backends

* Add changelog

* forgot about rtic-macros

* backend-specific configuration

* core peripherals optional over macro argument

* pre_init_preprocessing binding

* CI for RISC-V (WIP)

* separation of concerns

* add targets for RISC-V examples

* remove qemu feature

* prepare examples folder

* move examples all together

* move ci out of examples

* minor changes

* add cortex-m

* new xtask: proof of concept

* fix build.yml

* feature typo

* clean rtic examples

* reproduce weird issue

* remove unsafe code in user app

* update dependencies

* allow builds on riscv32imc

* let's fix QEMU

* Update .github/workflows/build.yml

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>

* New build.rs

* removing test features

* adapt ui test to new version of clippy

* add more examples to RISC-V backend

* proper configuration of heapless for riscv32imc

* opt-out examples for riscv32imc

* point to new version of riscv-slic

* adapt new macro bindings

* adapt examples and CI to stable

* fix cortex-m CI

* Review

---------

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>

1 files changed, 9 insertions, 2 deletions

diff --git a/rtic-macros/src/codegen/bindings.rs b/rtic-macros/src/codegen/bindings.rs
index 60605f3..501ccdf 100644
--- a/rtic-macros/src/codegen/bindings.rs
+++ b/rtic-macros/src/codegen/bindings.rs
@@ -2,7 +2,8 @@
     feature = "cortex-m-source-masking",
     feature = "cortex-m-basepri",
     feature = "test-template",
-    feature = "riscv-esp32c3"
+    feature = "riscv-esp32c3",
+    feature = "riscv-slic",
 )))]
 compile_error!("No backend selected");
 
@@ -22,4 +23,10 @@ mod template;
 pub use esp32c3::*;
 
 #[cfg(feature = "riscv-esp32c3")]
-mod esp32c3;
\ No newline at end of file
+mod esp32c3;
+
+#[cfg(feature = "riscv-slic")]
+pub use riscv_slic::*;
+
+#[cfg(feature = "riscv-slic")]
+mod riscv_slic;