diff options
| -rw-r--r-- | rtic-macros/src/codegen/bindings/esp32c6.rs | 18 | ||||
| -rw-r--r-- | rtic/src/export/riscv_esp32c6.rs | 36 |
2 files changed, 16 insertions, 38 deletions
diff --git a/rtic-macros/src/codegen/bindings/esp32c6.rs b/rtic-macros/src/codegen/bindings/esp32c6.rs index 8e0af33..1d22466 100644 --- a/rtic-macros/src/codegen/bindings/esp32c6.rs +++ b/rtic-macros/src/codegen/bindings/esp32c6.rs @@ -13,11 +13,10 @@ mod esp32c6 { use std::collections::HashSet; use syn::{parse, Attribute, Ident}; - // Section 1.6.2 technical reference manual specifies which interrupts can be configured. - const EXTERNAL_INTERRUPTS: [u8; 28] = [ - 1, 2, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, - 28, 29, 30, 31, - ]; + // esp-hal reserves interrupts 1-19: + // https://github.com/esp-rs/esp-hal/blob/esp-hal-v1.0.0-beta.0/esp-hal/src/interrupt/riscv.rs#L200 + // https://github.com/esp-rs/esp-hal/blob/esp-hal-v1.0.0-beta.0/esp-hal/src/interrupt/riscv.rs#L725 + const EXTERNAL_INTERRUPTS: [u8; 12] = [20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]; #[allow(clippy::too_many_arguments)] pub fn impl_mutex( @@ -243,12 +242,9 @@ mod esp32c6 { ) .zip(EXTERNAL_INTERRUPTS) { - // interrupt1...interrupt19 are already defined in esp_hal - if curr_cpu_id > 19 { - if *name == dispatcher_name { - let ret = &("interrupt".to_owned() + &curr_cpu_id.to_string()); - stmts.push(quote!(#[export_name = #ret])); - } + if *name == dispatcher_name { + let ret = &("interrupt".to_owned() + &curr_cpu_id.to_string()); + stmts.push(quote!(#[export_name = #ret])); } } diff --git a/rtic/src/export/riscv_esp32c6.rs b/rtic/src/export/riscv_esp32c6.rs index cf7ac3c..6789f26 100644 --- a/rtic/src/export/riscv_esp32c6.rs +++ b/rtic/src/export/riscv_esp32c6.rs @@ -1,5 +1,5 @@ pub use esp32c6::{Interrupt, Peripherals}; -use esp32c6::{INTERRUPT_CORE0, INTPRI, PLIC_MX}; +use esp32c6::{INTERRUPT_CORE0, PLIC_MX}; pub use riscv::interrupt; pub use riscv::register::mcause; @@ -148,32 +148,14 @@ pub fn enable(int: Interrupt, prio: u8, cpu_int_id: u8) { .offset(int as isize) .write_volatile(cpu_int_id as u32); - match int { - Interrupt::FROM_CPU_INTR0 - | Interrupt::FROM_CPU_INTR1 - | Interrupt::FROM_CPU_INTR2 - | Interrupt::FROM_CPU_INTR3 => { - // Set the interrupt's priority: - (*INTPRI::ptr()) - .cpu_int_pri(cpu_int_id as usize) - .write(|w| w.bits(prio as u32)); - - // Finally, enable the CPU interrupt: - (*INTPRI::ptr()) - .cpu_int_enable() - .modify(|r, w| w.bits((1 << cpu_int_id) | r.bits())); - } - _ => { - // Set the interrupt's priority: - (*PLIC_MX::ptr()) - .mxint_pri(cpu_int_id as usize) - .write(|w| w.bits(prio as u32)); + // Set the interrupt's priority: + (*PLIC_MX::ptr()) + .mxint_pri(cpu_int_id as usize) + .write(|w| w.bits(prio as u32)); - // Finally, enable the CPU interrupt: - (*PLIC_MX::ptr()) - .mxint_enable() - .modify(|r, w| w.bits((1 << cpu_int_id) | r.bits())); - } - } + // Finally, enable the CPU interrupt: + (*PLIC_MX::ptr()) + .mxint_enable() + .modify(|r, w| w.bits((1 << cpu_int_id) | r.bits())); } } |