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| -rw-r--r-- | book/en/src/internals/targets.md | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/book/en/src/internals/targets.md b/book/en/src/internals/targets.md index 65c0712..bdfb24b 100644 --- a/book/en/src/internals/targets.md +++ b/book/en/src/internals/targets.md @@ -2,10 +2,13 @@ While RTIC can currently target all Cortex-m devices there are some key architecure differences that users should be aware of. Namely the absence of Base Priority Mask Register (`BASEPRI`) which lends itself exceptionally well to the hardware priority ceiling support used in RTIC, in the -ARMv6-M and ARMv8-M-base architectures requires a few tweaks from RTIC to deliver the same -features. These differences result in two flavors of critical sections: priority ceiling, and source -masking. Table 1 below shows a list of Cortex-m processors and which type of critical section they -employ. +ARMv6-M and ARMv8-M-base architectures, which forces RTIC to use source masking instead. For each implementation of lock and a detailed commentary of pros and cons, see the implementation of [lock in src/export.rs][src_export]. + +[src_export]: https://github.com/rtic-rs/cortex-m-rtic/blob/master/src/export.rs + +These differences influence how critical sections are realized, but functionality should be the same except that ARMv6-M/ARMv8-M-base cannot have tasks with shared resources bound to exception handlers, as these cannot be masked in hardware. + +Table 1 below shows a list of Cortex-m processors and which type of critical section they employ. #### *Table 1: Critical Section Implementation by Processor Architecture* |