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| author | Katherine Temkin <k@ktemkin.com> | 2020-10-07 19:52:19 -0600 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-10-09 12:21:56 +0000 |
| commit | 65fc46c957174e877924c3f7d8e05a3006ff1a76 (patch) | |
| tree | 5c4e49abd84d0d46701b4e3c024b66baf5f46f8d | |
| parent | 434702fee6f9a5c71b4cddcf6110178603fe2209 (diff) | |
genesys2: correctly specify I/O attributes for VADJ banks
| -rw-r--r-- | nmigen_boards/genesys2.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py index b23976f..a82ceaa 100644 --- a/nmigen_boards/genesys2.py +++ b/nmigen_boards/genesys2.py @@ -24,7 +24,7 @@ class Genesys2Platform(Xilinx7SeriesPlatform): self._JP6 = JP6 def bank15_16_17_iostandard(self): - return "LVCMOS" + self._JP6 + return "LVCMOS" + self._JP6.replace('V', '') default_rst = "rst" default_clk = "clk" |