diff options
| -rw-r--r-- | nmigen_boards/genesys2.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py index b23976f..a82ceaa 100644 --- a/nmigen_boards/genesys2.py +++ b/nmigen_boards/genesys2.py @@ -24,7 +24,7 @@ class Genesys2Platform(Xilinx7SeriesPlatform): self._JP6 = JP6 def bank15_16_17_iostandard(self): - return "LVCMOS" + self._JP6 + return "LVCMOS" + self._JP6.replace('V', '') default_rst = "rst" default_clk = "clk" |