diff options
| author | Ivan Grokhotkov <ivan@espressif.com> | 2020-06-08 23:19:24 +0200 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-11 14:10:55 +0000 |
| commit | f3957586e210d6d7c7c40b8b4080107c28c1c744 (patch) | |
| tree | b08a2127f5edb8ef060b41200117b12d532b457e | |
| parent | 1acda441f977c61ab0a7e1edad563d8cefc52252 (diff) | |
[breaking-change] nexys4ddr: fix UART RTS/CTS pins.
According to the schematic, RTS is E5 and CTS is D3. Previously these
were reversed to work around signal direction set in UARTResource.
Un-reverse the signals, and set correct direction by passing role=dce.
Ref. https://reference.digilentinc.com/_media/nexys4-ddr:nexys_4_ddr_sch.pdf
| -rw-r--r-- | nmigen_boards/nexys4ddr.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/nmigen_boards/nexys4ddr.py b/nmigen_boards/nexys4ddr.py index 02dc101..f67979c 100644 --- a/nmigen_boards/nexys4ddr.py +++ b/nmigen_boards/nexys4ddr.py @@ -100,8 +100,9 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform): Attrs(IOSTANDARD="LVCMOS33")), UARTResource(0, - rx="C4", tx="D4", rts="D3", cts="E5", - attrs=Attrs(IOSTANDARD="LVCMOS33")), + rx="C4", tx="D4", rts="E5", cts="D3", + attrs=Attrs(IOSTANDARD="LVCMOS33"), + role="dce"), Resource("ps2_host", 0, Subsignal("clk", Pins("F4", dir="i")), |