diff options
| -rw-r--r-- | nmigen_boards/nexys4ddr.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/nmigen_boards/nexys4ddr.py b/nmigen_boards/nexys4ddr.py index 02dc101..f67979c 100644 --- a/nmigen_boards/nexys4ddr.py +++ b/nmigen_boards/nexys4ddr.py @@ -100,8 +100,9 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform): Attrs(IOSTANDARD="LVCMOS33")), UARTResource(0, - rx="C4", tx="D4", rts="D3", cts="E5", - attrs=Attrs(IOSTANDARD="LVCMOS33")), + rx="C4", tx="D4", rts="E5", cts="D3", + attrs=Attrs(IOSTANDARD="LVCMOS33"), + role="dce"), Resource("ps2_host", 0, Subsignal("clk", Pins("F4", dir="i")), |