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| author | ECP5-PCIe <65254322+ECP5-PCIe@users.noreply.github.com> | 2020-07-16 10:22:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-16 08:22:51 +0000 |
| commit | 19cf06052230831e6d899aa3cf71539fe746a43e (patch) | |
| tree | 6d138b34c46a822239879d31fc9d99b4e15b7a52 /nmigen_boards/arty_z7.py | |
| parent | 83d9ecdd47e6610ea71037e155a8e2fd51f9f19c (diff) | |
[breaking-change] Update SPI pin names.
The new names follow the OSHWA convention described at:
https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
Diffstat (limited to 'nmigen_boards/arty_z7.py')
| -rw-r--r-- | nmigen_boards/arty_z7.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/nmigen_boards/arty_z7.py b/nmigen_boards/arty_z7.py index d22022a..dfac87f 100644 --- a/nmigen_boards/arty_z7.py +++ b/nmigen_boards/arty_z7.py @@ -128,8 +128,8 @@ class ArtyZ720Platform(Xilinx7SeriesPlatform): }), Connector("ck_spi", 0, { - "miso": "W15", - "mosi": "T12", + "cipo": "W15", + "copi": "T12", "sck": "H15", "ss": "F16" }), |