diff options
28 files changed, 58 insertions, 58 deletions
diff --git a/nmigen_boards/arty_a7.py b/nmigen_boards/arty_a7.py index ba4a9db..b1defe1 100644 --- a/nmigen_boards/arty_a7.py +++ b/nmigen_boards/arty_a7.py @@ -36,7 +36,7 @@ class ArtyA7Platform(Xilinx7SeriesPlatform): Resource("cpu_reset", 0, Pins("C2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), SPIResource(0, - cs="C1", clk="F1", mosi="H1", miso="G1", + cs="C1", clk="F1", copi="H1", cipo="G1", attrs=Attrs(IOSTANDARD="LVCMOS33") ), @@ -49,7 +49,7 @@ class ArtyA7Platform(Xilinx7SeriesPlatform): ), *SPIFlashResources(0, - cs="L13", clk="L16", mosi="K17", miso="K18", wp="L14", hold="M14", + cs="L13", clk="L16", copi="K17", cipo="K18", wp="L14", hold="M14", attrs=Attrs(IOSTANDARD="LVCMOS33") ), diff --git a/nmigen_boards/arty_z7.py b/nmigen_boards/arty_z7.py index d22022a..dfac87f 100644 --- a/nmigen_boards/arty_z7.py +++ b/nmigen_boards/arty_z7.py @@ -128,8 +128,8 @@ class ArtyZ720Platform(Xilinx7SeriesPlatform): }), Connector("ck_spi", 0, { - "miso": "W15", - "mosi": "T12", + "cipo": "W15", + "copi": "T12", "sck": "H15", "ss": "F16" }), diff --git a/nmigen_boards/atlys.py b/nmigen_boards/atlys.py index 5f5a682..0f70ac6 100644 --- a/nmigen_boards/atlys.py +++ b/nmigen_boards/atlys.py @@ -71,7 +71,7 @@ class AtlysPlatform(XilinxSpartan6Platform): ), *SPIFlashResources(0, - cs="AE14", clk="AH18", mosi="AF14", miso="AF20", wp="AG21", hold="AG17", + cs="AE14", clk="AH18", copi="AF14", cipo="AF20", wp="AG21", hold="AG17", attrs=Attrs(IOSTANDARD="LVCMOS25", SLEW="FAST"), ), diff --git a/nmigen_boards/de10_nano.py b/nmigen_boards/de10_nano.py index 517f45d..f8d7470 100644 --- a/nmigen_boards/de10_nano.py +++ b/nmigen_boards/de10_nano.py @@ -40,7 +40,7 @@ class DE10NanoPlatform(IntelPlatform): # LTC2308 analogue-to-digital converter SPIResource(0, - cs="U9", clk="V10", mosi="AC4", miso="AD4", + cs="U9", clk="V10", copi="AC4", cipo="AD4", attrs=Attrs(io_standard="3.3-V LVTTL")), # ADV7513 HDMI transmitter diff --git a/nmigen_boards/ecp5_5g_evn.py b/nmigen_boards/ecp5_5g_evn.py index d0625de..c6090fc 100644 --- a/nmigen_boards/ecp5_5g_evn.py +++ b/nmigen_boards/ecp5_5g_evn.py @@ -70,7 +70,7 @@ class ECP55GEVNPlatform(LatticeECP5Platform): ), *SPIFlashResources(0, - cs="R2", clk="U3", miso="V2", mosi="W2", wp="Y2", hold="W1", + cs="R2", clk="U3", cipo="V2", copi="W2", wp="Y2", hold="W1", attrs=Attrs(IO_STANDARD="LVCMOS33") ), diff --git a/nmigen_boards/ecpix5.py b/nmigen_boards/ecpix5.py index de28a35..3425557 100644 --- a/nmigen_boards/ecpix5.py +++ b/nmigen_boards/ecpix5.py @@ -42,7 +42,7 @@ class _ECPIX5Platform(LatticeECP5Platform): ), *SPIFlashResources(0, - cs="AA2", clk="AE3", miso="AE2", mosi="AD2", wp="AF2", hold="AE1", + cs="AA2", clk="AE3", cipo="AE2", copi="AD2", wp="AF2", hold="AE1", attrs=Attrs(IO_TYPE="LVCMOS33") ), diff --git a/nmigen_boards/extensions/pmod.py b/nmigen_boards/extensions/pmod.py index 331352c..f265607 100644 --- a/nmigen_boards/extensions/pmod.py +++ b/nmigen_boards/extensions/pmod.py @@ -26,8 +26,8 @@ def PmodSPIType2Resource(name, number, *, pmod, extras=None): return Resource(name, number, Subsignal("cs_n", Pins("1", dir="o", conn=("pmod", pmod))), Subsignal("clk", Pins("2", dir="o", conn=("pmod", pmod))), - Subsignal("mosi", Pins("3", dir="o", conn=("pmod", pmod))), - Subsignal("miso", Pins("4", dir="i", conn=("pmod", pmod))), + Subsignal("copi", Pins("3", dir="o", conn=("pmod", pmod))), + Subsignal("cipo", Pins("4", dir="i", conn=("pmod", pmod))), extras=extras ) @@ -36,8 +36,8 @@ def PmodSPIType2AResource(name, number, *, pmod, extras=None): return Resource(name, number, Subsignal("cs_n", Pins("1", dir="o", conn=("pmod", pmod))), Subsignal("clk", Pins("2", dir="o", conn=("pmod", pmod))), - Subsignal("mosi", Pins("3", dir="o", conn=("pmod", pmod))), - Subsignal("miso", Pins("4", dir="i", conn=("pmod", pmod))), + Subsignal("copi", Pins("3", dir="o", conn=("pmod", pmod))), + Subsignal("cipo", Pins("4", dir="i", conn=("pmod", pmod))), Subsignal("int", Pins("7", dir="i", conn=("pmod", pmod))), Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))), extras=extras diff --git a/nmigen_boards/fomu_hacker.py b/nmigen_boards/fomu_hacker.py index 37dda34..8bc9308 100644 --- a/nmigen_boards/fomu_hacker.py +++ b/nmigen_boards/fomu_hacker.py @@ -31,7 +31,7 @@ class FomuHackerPlatform(LatticeICE40Platform): ), *SPIFlashResources(0, - cs="C1", clk="D1", mosi="F1", miso="E1", + cs="C1", clk="D1", copi="F1", cipo="E1", attrs=Attrs(IO_STANDARD="SB_LVCMOS"), ), ] diff --git a/nmigen_boards/fomu_pvt.py b/nmigen_boards/fomu_pvt.py index 4a2b1ba..ed8ff8f 100644 --- a/nmigen_boards/fomu_pvt.py +++ b/nmigen_boards/fomu_pvt.py @@ -31,7 +31,7 @@ class FomuPVTPlatform(LatticeICE40Platform): ), *SPIFlashResources(0, - cs="C1", clk="D1", mosi="F1", miso="E1", + cs="C1", clk="D1", copi="F1", cipo="E1", attrs=Attrs(IO_STANDARD="SB_LVCMOS"), ), diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py index 66525fd..b23976f 100644 --- a/nmigen_boards/genesys2.py +++ b/nmigen_boards/genesys2.py @@ -99,8 +99,8 @@ class Genesys2Platform(Xilinx7SeriesPlatform): Resource("audio_clk", 0, # ADAU1761 MCLK Pins("AK19", dir="o"), Attrs(IOSTANDARD="LVCMOS18")), SPIResource(0, # OLED, SSD1306, 128 x 32 - cs="dummy-cs0", clk="AF17", mosi="Y15", - miso="dummy-miso0", reset="AB17", + cs="dummy-cs0", clk="AF17", copi="Y15", + cipo="dummy-cipo0", reset="AB17", attrs=Attrs(IOSTANDARD="LVCMOS18")), Resource("oled", 0, # OLED, UG-2832HSWEG04 Subsignal("dc", Pins("AC17", dir="o")), diff --git a/nmigen_boards/ice40_hx1k_blink_evn.py b/nmigen_boards/ice40_hx1k_blink_evn.py index 03d91a0..b2542cf 100644 --- a/nmigen_boards/ice40_hx1k_blink_evn.py +++ b/nmigen_boards/ice40_hx1k_blink_evn.py @@ -25,7 +25,7 @@ class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform): Resource("touch", 3, Pins("52"), Attrs(IO_STANDARD="SB_LVCMOS")), *SPIFlashResources(0, - cs="49", clk="48", mosi="45", miso="46", + cs="49", clk="48", copi="45", cipo="46", attrs=Attrs(IO_STANDARD="SB_LVCMOS") ), ] diff --git a/nmigen_boards/ice40_hx8k_b_evn.py b/nmigen_boards/ice40_hx8k_b_evn.py index 48d5d9e..635cab4 100644 --- a/nmigen_boards/ice40_hx8k_b_evn.py +++ b/nmigen_boards/ice40_hx8k_b_evn.py @@ -29,7 +29,7 @@ class ICE40HX8KBEVNPlatform(LatticeICE40Platform): ), *SPIFlashResources(0, - cs="R12", clk="R11", mosi="P12", miso="P11", + cs="R12", clk="R11", copi="P12", cipo="P11", attrs=Attrs(IO_STANDARD="SB_LVCMOS") ), ] diff --git a/nmigen_boards/ice40_up5k_b_evn.py b/nmigen_boards/ice40_up5k_b_evn.py index e931790..d6254cb 100644 --- a/nmigen_boards/ice40_up5k_b_evn.py +++ b/nmigen_boards/ice40_up5k_b_evn.py @@ -38,7 +38,7 @@ class ICE40UP5KBEVNPlatform(LatticeICE40Platform): ), *SPIFlashResources(0, - cs="16", clk="15", mosi="14", miso="17", + cs="16", clk="15", copi="14", cipo="17", attrs=Attrs(IO_STANDARD="SB_LVCMOS") ), ] diff --git a/nmigen_boards/icebreaker.py b/nmigen_boards/icebreaker.py index 0877031..ecdfe1a 100644 --- a/nmigen_boards/icebreaker.py +++ b/nmigen_boards/icebreaker.py @@ -30,7 +30,7 @@ class ICEBreakerPlatform(LatticeICE40Platform): ), *SPIFlashResources(0, - cs="16", clk="15", mosi="14", miso="17", wp="12", hold="13", + cs="16", clk="15", copi="14", cipo="17", wp="12", hold="13", attrs=Attrs(IO_STANDARD="SB_LVCMOS") ), ] diff --git a/nmigen_boards/icestick.py b/nmigen_boards/icestick.py index 257e623..8104aff 100644 --- a/nmigen_boards/icestick.py +++ b/nmigen_boards/icestick.py @@ -31,7 +31,7 @@ class ICEStickPlatform(LatticeICE40Platform): ), *SPIFlashResources(0, - cs="71", clk="70", mosi="67", miso="68", + cs="71", clk="70", copi="67", cipo="68", attrs=Attrs(IO_STANDARD="SB_LVCMOS") ), ] diff --git a/nmigen_boards/machxo3_sk.py b/nmigen_boards/machxo3_sk.py index a1f8540..fcd769b 100644 --- a/nmigen_boards/machxo3_sk.py +++ b/nmigen_boards/machxo3_sk.py @@ -36,7 +36,7 @@ class MachXO3SKPlatform(LatticeMachXO3LPlatform): ), # SW2 *SPIFlashResources(0, - cs="R5", clk="P6", mosi="T13", miso="T6", + cs="R5", clk="P6", copi="T13", cipo="T6", attrs=Attrs(IO_TYPE="LVCMOS33") ), ] diff --git a/nmigen_boards/mercury.py b/nmigen_boards/mercury.py index 5daf802..c0bd107 100644 --- a/nmigen_boards/mercury.py +++ b/nmigen_boards/mercury.py @@ -40,19 +40,19 @@ class MercuryPlatform(XilinxSpartan3APlatform): # The serial interface and flash memory have a shared SPI bus. # FPGA is secondary. SPIResource("spi_serial", 0, role="device", - cs="P39", clk="P53", mosi="P46", miso="P51", + cs="P39", clk="P53", copi="P46", cipo="P51", attrs=Attrs(IOSTANDARD="LVTTL"), ), # FPGA is primary. *SPIFlashResources(0, - cs="P27", clk="P53", mosi="P46", miso="P51", + cs="P27", clk="P53", copi="P46", cipo="P51", attrs=Attrs(IOSTANDARD="LVTTL") ), # ADC over SPI- FPGA is primary. SPIResource("spi_adc", 0, role="host", - cs="P12", clk="P9", mosi="P10", miso="P21", + cs="P12", clk="P9", copi="P10", cipo="P21", attrs=Attrs(IOSTANDARD="LVTTL"), ), diff --git a/nmigen_boards/mister.py b/nmigen_boards/mister.py index b613e99..2eacedf 100644 --- a/nmigen_boards/mister.py +++ b/nmigen_boards/mister.py @@ -40,7 +40,7 @@ class MisterPlatform(IntelPlatform): # LTC2308 analogue-to-digital converter SPIResource(0, - cs="U9", clk="V10", mosi="AC4", miso="AD4", + cs="U9", clk="V10", copi="AC4", cipo="AD4", attrs=Attrs(io_standard="3.3-V LVTTL")), # ADV7513 HDMI transmitter diff --git a/nmigen_boards/nexys4ddr.py b/nmigen_boards/nexys4ddr.py index f67979c..d4da078 100644 --- a/nmigen_boards/nexys4ddr.py +++ b/nmigen_boards/nexys4ddr.py @@ -75,8 +75,8 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform): Resource("accelerometer", 0, # ADXL362 Subsignal("cs", PinsN("D15", dir="o")), Subsignal("clk", Pins("F15", dir="o")), - Subsignal("mosi", Pins("F14", dir="o")), - Subsignal("miso", Pins("E15", dir="i")), + Subsignal("copi", Pins("F14", dir="o")), + Subsignal("cipo", Pins("E15", dir="i")), Subsignal("int", Pins("B13 C16", dir="i"), Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")), Attrs(IOSTANDARD="LVCMOS33")), @@ -123,7 +123,7 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform): Attrs(IOSTANDARD="LVCMOS33")), *SPIFlashResources(0, - cs="L13", clk="E9", mosi="K17", miso="K18", wp="L14", hold="M14", + cs="L13", clk="E9", copi="K17", cipo="K18", wp="L14", hold="M14", attrs=Attrs(IOSTANDARD="LVCMOS33")), Resource("ddr2", 0, # MT47H64M16HR-25:H diff --git a/nmigen_boards/numato_mimas.py b/nmigen_boards/numato_mimas.py index 2e76c69..2e7b78c 100644 --- a/nmigen_boards/numato_mimas.py +++ b/nmigen_boards/numato_mimas.py @@ -24,7 +24,7 @@ class NumatoMimasPlatform(XilinxSpartan6Platform): attrs=Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")), *SPIFlashResources(0, - cs="P38", clk="P70", mosi="P64", miso="65", + cs="P38", clk="P70", copi="P64", cipo="65", attrs=Attrs(IOSTANDARD="LVCMOS33") ), ] diff --git a/nmigen_boards/orangecrab_r0_1.py b/nmigen_boards/orangecrab_r0_1.py index d9964d3..abd9c7d 100644 --- a/nmigen_boards/orangecrab_r0_1.py +++ b/nmigen_boards/orangecrab_r0_1.py @@ -28,7 +28,7 @@ class OrangeCrabR0_1Platform(LatticeECP5Platform): attrs=Attrs(IO_TYPE="LVCMOS33")), *SPIFlashResources(0, - cs="U17", clk="U16", miso="T18", mosi="U18", wp="R18", hold="N18", + cs="U17", clk="U16", cipo="T18", copi="U18", wp="R18", hold="N18", attrs=Attrs(IO_TYPE="LVCMOS33"), ), @@ -82,8 +82,8 @@ class OrangeCrabR0_1Platform(LatticeECP5Platform): "11": "A8", "12": "H2", "13": "J2", - "miso": "N15", - "mosi": "N16", + "cipo": "N15", + "copi": "N16", "sck": "R17", "scl": "C9", "sda": "C10" diff --git a/nmigen_boards/orangecrab_r0_2.py b/nmigen_boards/orangecrab_r0_2.py index 8853cbc..ccd48f4 100644 --- a/nmigen_boards/orangecrab_r0_2.py +++ b/nmigen_boards/orangecrab_r0_2.py @@ -32,7 +32,7 @@ class OrangeCrabR0_2Platform(LatticeECP5Platform): attrs=Attrs(IO_TYPE="SSTL135_I")), *SPIFlashResources(0, - cs="U17", clk="U16", miso="T18", mosi="U18", wp="R18", hold="N18", + cs="U17", clk="U16", cipo="T18", copi="U18", wp="R18", hold="N18", attrs=Attrs(IO_TYPE="LVCMOS33"), ), @@ -99,8 +99,8 @@ class OrangeCrabR0_2Platform(LatticeECP5Platform): "a2": "N4", "a3": "H4", "a4": "G4", - "miso": "N15", - "mosi": "N16", + "cipo": "N15", + "copi": "N16", "sck": "R17", "scl": "C9", "sda": "C10" diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py index 848e1b8..9073cc7 100644 --- a/nmigen_boards/resources/interface.py +++ b/nmigen_boards/resources/interface.py @@ -53,28 +53,28 @@ def IrDAResource(number, *, rx, tx, en=None, sd=None, return Resource("irda", number, *io) -def SPIResource(*args, cs, clk, mosi, miso, int=None, reset=None, - conn=None, attrs=None, role="host"): - assert role in ("host", "device") +def SPIResource(*args, cs, clk, copi, cipo, int=None, reset=None, + conn=None, attrs=None, role="controller"): + assert role in ("controller", "peripheral") io = [] - if role == "host": + if role == "controller": io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn))) io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1))) - io.append(Subsignal("mosi", Pins(mosi, dir="o", conn=conn, assert_width=1))) - io.append(Subsignal("miso", Pins(miso, dir="i", conn=conn, assert_width=1))) - else: # device + io.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1))) + io.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1))) + else: # peripheral io.append(Subsignal("cs", PinsN(cs, dir="i", conn=conn, assert_width=1))) io.append(Subsignal("clk", Pins(clk, dir="i", conn=conn, assert_width=1))) - io.append(Subsignal("mosi", Pins(mosi, dir="i", conn=conn, assert_width=1))) - io.append(Subsignal("miso", Pins(miso, dir="oe", conn=conn, assert_width=1))) + io.append(Subsignal("copi", Pins(copi, dir="i", conn=conn, assert_width=1))) + io.append(Subsignal("cipo", Pins(cipo, dir="oe", conn=conn, assert_width=1))) if int is not None: - if role == "host": + if role == "controller": io.append(Subsignal("int", Pins(int, dir="i", conn=conn))) else: io.append(Subsignal("int", Pins(int, dir="oe", conn=conn, assert_width=1))) if reset is not None: - if role == "host": + if role == "controller": io.append(Subsignal("reset", Pins(reset, dir="o", conn=conn))) else: io.append(Subsignal("reset", Pins(reset, dir="i", conn=conn, assert_width=1))) diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py index 7f45cad..160f3df 100644 --- a/nmigen_boards/resources/memory.py +++ b/nmigen_boards/resources/memory.py @@ -7,7 +7,7 @@ __all__ = [ ] -def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, +def SPIFlashResources(*args, cs, clk, copi, cipo, wp=None, hold=None, conn=None, attrs=None): resources = [] @@ -18,8 +18,8 @@ def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1))) io_1x = list(io_all) - io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", conn=conn, assert_width=1))) - io_1x.append(Subsignal("miso", Pins(miso, dir="i", conn=conn, assert_width=1))) + io_1x.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1))) + io_1x.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1))) if wp is not None and hold is not None: io_1x.append(Subsignal("wp", PinsN(wp, dir="o", conn=conn, assert_width=1))) io_1x.append(Subsignal("hold", PinsN(hold, dir="o", conn=conn, assert_width=1))) @@ -27,14 +27,14 @@ def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, name_suffix="1x")) io_2x = list(io_all) - io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io", conn=conn, + io_2x.append(Subsignal("dq", Pins(" ".join([copi, cipo]), dir="io", conn=conn, assert_width=2))) resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x, name_suffix="2x")) if wp is not None and hold is not None: io_4x = list(io_all) - io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io", conn=conn, + io_4x.append(Subsignal("dq", Pins(" ".join([copi, cipo, wp, hold]), dir="io", conn=conn, assert_width=4))) resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x, name_suffix="4x")) @@ -78,8 +78,8 @@ def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=N # DAT3/CS# has a pullup and doubles as electronic card detect io_spi.append(Subsignal("cs", PinsN(dat3, dir="io", conn=conn, assert_width=1))) io_spi.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1))) - io_spi.append(Subsignal("mosi", Pins(cmd, dir="o", conn=conn, assert_width=1))) - io_spi.append(Subsignal("miso", Pins(dat0, dir="i", conn=conn, assert_width=1))) + io_spi.append(Subsignal("copi", Pins(cmd, dir="o", conn=conn, assert_width=1))) + io_spi.append(Subsignal("cipo", Pins(dat0, dir="i", conn=conn, assert_width=1))) resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi, name_suffix="spi")) diff --git a/nmigen_boards/sk_xc6slx9.py b/nmigen_boards/sk_xc6slx9.py index cec6d2f..d9acdc2 100644 --- a/nmigen_boards/sk_xc6slx9.py +++ b/nmigen_boards/sk_xc6slx9.py @@ -20,7 +20,7 @@ class SK_XC6SLX9Platform(XilinxSpartan6Platform): ), *SPIFlashResources(0, - cs="P38", clk="P70", mosi="P64", miso="65", + cs="P38", clk="P70", copi="P64", cipo="65", attrs=Attrs(IOSTANDARD="LVCMOS33") ), diff --git a/nmigen_boards/tinyfpga_bx.py b/nmigen_boards/tinyfpga_bx.py index ede0858..1606f17 100644 --- a/nmigen_boards/tinyfpga_bx.py +++ b/nmigen_boards/tinyfpga_bx.py @@ -27,7 +27,7 @@ class TinyFPGABXPlatform(LatticeICE40Platform): ), *SPIFlashResources(0, - cs="F7", clk="G7", mosi="G6", miso="H7", wp="H4", hold="J8", + cs="F7", clk="G7", copi="G6", cipo="H7", wp="H4", hold="J8", attrs=Attrs(IO_STANDARD="SB_LVCMOS") ), ] diff --git a/nmigen_boards/upduino_v1.py b/nmigen_boards/upduino_v1.py index 6790450..6f5a0d6 100644 --- a/nmigen_boards/upduino_v1.py +++ b/nmigen_boards/upduino_v1.py @@ -22,7 +22,7 @@ class UpduinoV1Platform(LatticeICE40Platform): Attrs(IO_STANDARD="SB_LVCMOS")), *SPIFlashResources(0, - cs="16", clk="15", miso="17", mosi="14", + cs="16", clk="15", cipo="17", copi="14", attrs=Attrs(IO_STANDARD="SB_LVCMOS") ), ] diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py index 9384bb9..6258b53 100644 --- a/nmigen_boards/versa_ecp5.py +++ b/nmigen_boards/versa_ecp5.py @@ -55,7 +55,7 @@ class VersaECP5Platform(LatticeECP5Platform): ), *SPIFlashResources(0, - cs="R2", clk="U3", miso="W2", mosi="V2", wp="Y2", hold="W1", + cs="R2", clk="U3", cipo="W2", copi="V2", wp="Y2", hold="W1", attrs=Attrs(IO_STANDARD="LVCMOS33") ), |