diff options
| author | whitequark <whitequark@whitequark.org> | 2019-06-28 03:33:41 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-06-28 03:37:11 +0000 |
| commit | b2af7361c1863c4b6699b21c4b06935edd3671b8 (patch) | |
| tree | 88fd035bdb18a057a0fb21539280a67781450d39 /nmigen_boards/blackice.py | |
| parent | c2a8e9adbce74078f0a147e4cce87ff1b7c2fb8e (diff) | |
[breaking-change] Factor out "serial" resource and rename to "uart".
Also, add missing pullups where appropriate.
Diffstat (limited to 'nmigen_boards/blackice.py')
| -rw-r--r-- | nmigen_boards/blackice.py | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/nmigen_boards/blackice.py b/nmigen_boards/blackice.py index 91c1e01..399e29c 100644 --- a/nmigen_boards/blackice.py +++ b/nmigen_boards/blackice.py @@ -3,6 +3,7 @@ import subprocess from nmigen.build import * from nmigen.vendor.lattice_ice40 import * +from .dev import * __all__ = ["BlackIcePlatform"] @@ -34,12 +35,9 @@ class BlackIcePlatform(LatticeICE40Platform): Resource("user_sw", 2, PinsN("39", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")), Resource("user_sw", 3, PinsN("41", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")), - Resource("serial", 0, - Subsignal("rx", Pins("88", dir="i")), - Subsignal("tx", Pins("85", dir="o")), - Subsignal("rts", Pins("91", dir="o")), - Subsignal("cts", Pins("94", dir="i")), - Attrs(IO_STANDARD="SB_LVCMOS33"), + UARTResource(0, + rx="88", tx="85", rts="91", cts="94", + attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1") ), Resource("sram", 0, |