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authorwhitequark <whitequark@whitequark.org>2019-06-28 03:33:41 +0000
committerwhitequark <whitequark@whitequark.org>2019-06-28 03:37:11 +0000
commitb2af7361c1863c4b6699b21c4b06935edd3671b8 (patch)
tree88fd035bdb18a057a0fb21539280a67781450d39 /nmigen_boards/blackice_ii.py
parentc2a8e9adbce74078f0a147e4cce87ff1b7c2fb8e (diff)
[breaking-change] Factor out "serial" resource and rename to "uart".
Also, add missing pullups where appropriate.
Diffstat (limited to 'nmigen_boards/blackice_ii.py')
-rw-r--r--nmigen_boards/blackice_ii.py9
1 files changed, 3 insertions, 6 deletions
diff --git a/nmigen_boards/blackice_ii.py b/nmigen_boards/blackice_ii.py
index ad8cf0f..35f3fe6 100644
--- a/nmigen_boards/blackice_ii.py
+++ b/nmigen_boards/blackice_ii.py
@@ -34,12 +34,9 @@ class BlackIceIIPlatform(LatticeICE40Platform):
Resource("user_sw", 2, PinsN("39", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_sw", 3, PinsN("41", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
- Resource("serial", 0,
- Subsignal("rx", Pins("88", dir="i")),
- Subsignal("tx", Pins("85", dir="o")),
- Subsignal("rts", Pins("91", dir="o")),
- Subsignal("cts", Pins("94", dir="i")),
- Attrs(IO_STANDARD="SB_LVCMOS33"),
+ UARTResource(0,
+ rx="88", tx="85", rts="91", cts="94",
+ attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
),
Resource("sram", 0,