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authorwhitequark <whitequark@whitequark.org>2019-10-03 05:54:12 +0000
committerwhitequark <whitequark@whitequark.org>2019-10-03 06:16:18 +0000
commitc7c637043817eae6f48c33b707b40c9c1b20f199 (patch)
tree3fa379b97128ad93a7c98c5da7e578605828cd6c /nmigen_boards/dev/sram.py
parentb033d53db305eb3f0aef336568cd69f8e8c536e1 (diff)
Reorganize resource taxonomy.
The current hierarchy isn't particularly well suited to resources like SDRAM or NOR flash, so make it much less fine-grained but easier to use and less nitpicky.
Diffstat (limited to 'nmigen_boards/dev/sram.py')
-rw-r--r--nmigen_boards/dev/sram.py20
1 files changed, 0 insertions, 20 deletions
diff --git a/nmigen_boards/dev/sram.py b/nmigen_boards/dev/sram.py
deleted file mode 100644
index 14e31ce..0000000
--- a/nmigen_boards/dev/sram.py
+++ /dev/null
@@ -1,20 +0,0 @@
-from nmigen.build import *
-
-
-__all__ = ["SRAMResource"]
-
-
-def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
- io = []
- io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
- if oe is not None:
- # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
- io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
- io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
- io.append(Subsignal("a", Pins(a, dir="o")))
- io.append(Subsignal("d", Pins(d, dir="io")))
- if dm is not None:
- io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#"
- if attrs is not None:
- io.append(attrs)
- return Resource.family(*args, default_name="sram", ios=io)