diff options
| author | whitequark <whitequark@whitequark.org> | 2019-06-28 03:33:41 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-06-28 03:37:11 +0000 |
| commit | b2af7361c1863c4b6699b21c4b06935edd3671b8 (patch) | |
| tree | 88fd035bdb18a057a0fb21539280a67781450d39 /nmigen_boards/dev/uart.py | |
| parent | c2a8e9adbce74078f0a147e4cce87ff1b7c2fb8e (diff) | |
[breaking-change] Factor out "serial" resource and rename to "uart".
Also, add missing pullups where appropriate.
Diffstat (limited to 'nmigen_boards/dev/uart.py')
| -rw-r--r-- | nmigen_boards/dev/uart.py | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/nmigen_boards/dev/uart.py b/nmigen_boards/dev/uart.py new file mode 100644 index 0000000..27d1c81 --- /dev/null +++ b/nmigen_boards/dev/uart.py @@ -0,0 +1,26 @@ +from nmigen.build import * + + +__all__ = ["UARTResource"] + + +def UARTResource(number, *, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None, + attrs=None): + io = [] + io.append(Subsignal("rx", Pins(rx, dir="i"))) + io.append(Subsignal("tx", Pins(rx, dir="o"))) + if rts is not None: + io.append(Subsignal("rts", Pins(rts, dir="o"))) + if cts is not None: + io.append(Subsignal("cts", Pins(cts, dir="i"))) + if dtr is not None: + io.append(Subsignal("dtr", Pins(dtr, dir="o"))) + if dsr is not None: + io.append(Subsignal("dsr", Pins(dsr, dir="i"))) + if dcd is not None: + io.append(Subsignal("dcd", Pins(dcd, dir="i"))) + if ri is not None: + io.append(Subsignal("ri", Pins(ri, dir="i"))) + if attrs is not None: + io.append(attrs) + return Resource("uart", number, *io) |
