diff options
| author | whitequark <whitequark@whitequark.org> | 2019-10-03 05:54:12 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-10-03 06:16:18 +0000 |
| commit | c7c637043817eae6f48c33b707b40c9c1b20f199 (patch) | |
| tree | 3fa379b97128ad93a7c98c5da7e578605828cd6c /nmigen_boards/dev/uart.py | |
| parent | b033d53db305eb3f0aef336568cd69f8e8c536e1 (diff) | |
Reorganize resource taxonomy.
The current hierarchy isn't particularly well suited to resources
like SDRAM or NOR flash, so make it much less fine-grained but easier
to use and less nitpicky.
Diffstat (limited to 'nmigen_boards/dev/uart.py')
| -rw-r--r-- | nmigen_boards/dev/uart.py | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/nmigen_boards/dev/uart.py b/nmigen_boards/dev/uart.py deleted file mode 100644 index 706e50c..0000000 --- a/nmigen_boards/dev/uart.py +++ /dev/null @@ -1,42 +0,0 @@ -from nmigen.build import * - - -__all__ = ["UARTResource", "IrDAResource"] - - -def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None, - attrs=None): - io = [] - io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1))) - io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1))) - if rts is not None: - io.append(Subsignal("rts", Pins(rts, dir="o", assert_width=1))) - if cts is not None: - io.append(Subsignal("cts", Pins(cts, dir="i", assert_width=1))) - if dtr is not None: - io.append(Subsignal("dtr", Pins(dtr, dir="o", assert_width=1))) - if dsr is not None: - io.append(Subsignal("dsr", Pins(dsr, dir="i", assert_width=1))) - if dcd is not None: - io.append(Subsignal("dcd", Pins(dcd, dir="i", assert_width=1))) - if ri is not None: - io.append(Subsignal("ri", Pins(ri, dir="i", assert_width=1))) - if attrs is not None: - io.append(attrs) - return Resource.family(*args, default_name="uart", ios=io) - - -def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None): - # Exactly one of en (active-high enable) or sd (shutdown, active-low enable) should - # be specified, and it is mapped to a logic level en subsignal. - assert (en is not None) ^ (sd is not None) - io = [] - io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1))) - io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1))) - if en is not None: - io.append(Subsignal("en", Pins(en, dir="o", assert_width=1))) - if sd is not None: - io.append(Subsignal("en", PinsN(sd, dir="o", assert_width=1))) - if attrs is not None: - io.append(attrs) - return Resource("irda", number, *io) |
