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authorwhitequark <whitequark@whitequark.org>2019-06-28 03:33:41 +0000
committerwhitequark <whitequark@whitequark.org>2019-06-28 03:37:11 +0000
commitb2af7361c1863c4b6699b21c4b06935edd3671b8 (patch)
tree88fd035bdb18a057a0fb21539280a67781450d39 /nmigen_boards/icestick.py
parentc2a8e9adbce74078f0a147e4cce87ff1b7c2fb8e (diff)
[breaking-change] Factor out "serial" resource and rename to "uart".
Also, add missing pullups where appropriate.
Diffstat (limited to 'nmigen_boards/icestick.py')
-rw-r--r--nmigen_boards/icestick.py12
1 files changed, 3 insertions, 9 deletions
diff --git a/nmigen_boards/icestick.py b/nmigen_boards/icestick.py
index 778ad2d..5d0dd4b 100644
--- a/nmigen_boards/icestick.py
+++ b/nmigen_boards/icestick.py
@@ -22,15 +22,9 @@ class ICEStickPlatform(LatticeICE40Platform):
Resource("user_led", 3, Pins("96", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_led", 4, Pins("95", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
- Resource("serial", 0,
- Subsignal("rx", Pins("9", dir="i")),
- Subsignal("tx", Pins("8", dir="o")),
- Subsignal("rts", Pins("7", dir="o")),
- Subsignal("cts", Pins("4", dir="i")),
- Subsignal("dtr", Pins("3", dir="o")),
- Subsignal("dsr", Pins("2", dir="i")),
- Subsignal("dcd", Pins("1", dir="i")),
- Attrs(IO_STANDARD="SB_LVTTL", PULLUP="1")
+ UARTResource(0,
+ rx="9", tx="8", rts="7", cts="4", dtr="3", dsr="2", dcd="1",
+ attrs=Attrs(IO_STANDARD="SB_LVTTL", PULLUP="1")
),
Resource("irda", 0,