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authorGuzTech <GuzTech@users.noreply.github.com>2020-11-26 15:50:00 +0100
committerGitHub <noreply@github.com>2020-11-26 14:50:00 +0000
commitb40c3d6cb20081ff8941fc4addef92170ffb01a9 (patch)
tree77ec275eeedadcce9a0b621cb4ae5c8db32211a3 /nmigen_boards/mercury.py
parentb90a89da7c3878ee10db3cb2d10f13aa2bbb85c3 (diff)
[breaking-change] Add `_n` suffix to argument names of pins with fixed inverters.
Note: this change does NOT affect pin functionality or naming, and does not require modifying your design. It does however affect some board files, where keywords corresponding to active low pins will have to be adjusted: SPIResource(0, cs="C1", ...) → SPIResource(0, cs_n="C1", ...) The new naming scheme will make it easier to write and audit board files by clearly marking inverted pins in resource factories, similarly to how `PinsN` indicates the same in bare resources. Fixes #129.
Diffstat (limited to 'nmigen_boards/mercury.py')
-rw-r--r--nmigen_boards/mercury.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/nmigen_boards/mercury.py b/nmigen_boards/mercury.py
index 98b1f7b..6750921 100644
--- a/nmigen_boards/mercury.py
+++ b/nmigen_boards/mercury.py
@@ -40,19 +40,19 @@ class MercuryPlatform(XilinxSpartan3APlatform):
# The serial interface and flash memory have a shared SPI bus.
# FPGA is secondary.
SPIResource("spi_serial", 0, role="peripheral",
- cs="P39", clk="P53", copi="P46", cipo="P51",
+ cs_n="P39", clk="P53", copi="P46", cipo="P51",
attrs=Attrs(IOSTANDARD="LVTTL"),
),
# FPGA is primary.
*SPIFlashResources(0,
- cs="P27", clk="P53", copi="P46", cipo="P51",
+ cs_n="P27", clk="P53", copi="P46", cipo="P51",
attrs=Attrs(IOSTANDARD="LVTTL")
),
# ADC over SPI- FPGA is primary.
SPIResource("spi_adc", 0, role="controller",
- cs="P12", clk="P9", copi="P10", cipo="P21",
+ cs_n="P12", clk="P9", copi="P10", cipo="P21",
attrs=Attrs(IOSTANDARD="LVTTL"),
),
@@ -101,7 +101,7 @@ class MercuryPlatform(XilinxSpartan3APlatform):
sram = [
SRAMResource(0,
- cs="P3", we="gpio_0:29",
+ cs_n="P3", we_n="gpio_0:29",
# According to the schematic, A19/Pin 25 on the SRAM is wired to
# gpio-0:20. However, according to the SRAM's datasheet, pin 25 is
# a NC. Do not expose for now.