diff options
| author | ECP5-PCIe <65254322+ECP5-PCIe@users.noreply.github.com> | 2020-07-16 10:22:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-16 08:22:51 +0000 |
| commit | 19cf06052230831e6d899aa3cf71539fe746a43e (patch) | |
| tree | 6d138b34c46a822239879d31fc9d99b4e15b7a52 /nmigen_boards/nexys4ddr.py | |
| parent | 83d9ecdd47e6610ea71037e155a8e2fd51f9f19c (diff) | |
[breaking-change] Update SPI pin names.
The new names follow the OSHWA convention described at:
https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
Diffstat (limited to 'nmigen_boards/nexys4ddr.py')
| -rw-r--r-- | nmigen_boards/nexys4ddr.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/nmigen_boards/nexys4ddr.py b/nmigen_boards/nexys4ddr.py index f67979c..d4da078 100644 --- a/nmigen_boards/nexys4ddr.py +++ b/nmigen_boards/nexys4ddr.py @@ -75,8 +75,8 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform): Resource("accelerometer", 0, # ADXL362 Subsignal("cs", PinsN("D15", dir="o")), Subsignal("clk", Pins("F15", dir="o")), - Subsignal("mosi", Pins("F14", dir="o")), - Subsignal("miso", Pins("E15", dir="i")), + Subsignal("copi", Pins("F14", dir="o")), + Subsignal("cipo", Pins("E15", dir="i")), Subsignal("int", Pins("B13 C16", dir="i"), Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")), Attrs(IOSTANDARD="LVCMOS33")), @@ -123,7 +123,7 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform): Attrs(IOSTANDARD="LVCMOS33")), *SPIFlashResources(0, - cs="L13", clk="E9", mosi="K17", miso="K18", wp="L14", hold="M14", + cs="L13", clk="E9", copi="K17", cipo="K18", wp="L14", hold="M14", attrs=Attrs(IOSTANDARD="LVCMOS33")), Resource("ddr2", 0, # MT47H64M16HR-25:H |