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authorGuzTech <GuzTech@users.noreply.github.com>2020-11-26 15:50:00 +0100
committerGitHub <noreply@github.com>2020-11-26 14:50:00 +0000
commitb40c3d6cb20081ff8941fc4addef92170ffb01a9 (patch)
tree77ec275eeedadcce9a0b621cb4ae5c8db32211a3 /nmigen_boards/resources/interface.py
parentb90a89da7c3878ee10db3cb2d10f13aa2bbb85c3 (diff)
[breaking-change] Add `_n` suffix to argument names of pins with fixed inverters.
Note: this change does NOT affect pin functionality or naming, and does not require modifying your design. It does however affect some board files, where keywords corresponding to active low pins will have to be adjusted: SPIResource(0, cs="C1", ...) → SPIResource(0, cs_n="C1", ...) The new naming scheme will make it easier to write and audit board files by clearly marking inverted pins in resource factories, similarly to how `PinsN` indicates the same in bare resources. Fixes #129.
Diffstat (limited to 'nmigen_boards/resources/interface.py')
-rw-r--r--nmigen_boards/resources/interface.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py
index 8d5bd7e..0e0118a 100644
--- a/nmigen_boards/resources/interface.py
+++ b/nmigen_boards/resources/interface.py
@@ -56,21 +56,21 @@ def IrDAResource(number, *, rx, tx, en=None, sd=None,
return Resource("irda", number, *io)
-def SPIResource(*args, cs, clk, copi, cipo, int=None, reset=None,
+def SPIResource(*args, cs_n, clk, copi, cipo, int=None, reset=None,
conn=None, attrs=None, role="controller"):
assert role in ("controller", "peripheral")
assert copi is not None or cipo is not None # support unidirectional SPI
io = []
if role == "controller":
- io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn)))
+ io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn)))
io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
if copi is not None:
io.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
if cipo is not None:
io.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
else: # peripheral
- io.append(Subsignal("cs", PinsN(cs, dir="i", conn=conn, assert_width=1)))
+ io.append(Subsignal("cs", PinsN(cs_n, dir="i", conn=conn, assert_width=1)))
io.append(Subsignal("clk", Pins(clk, dir="i", conn=conn, assert_width=1)))
if copi is not None:
io.append(Subsignal("copi", Pins(copi, dir="i", conn=conn, assert_width=1)))