diff options
| author | whitequark <whitequark@whitequark.org> | 2020-07-02 01:56:53 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-07-02 01:57:16 +0000 |
| commit | 95c1760cc87770b9dba8997c08508541a8cbec95 (patch) | |
| tree | 1b2f9a5ec5938148f6280ae2c5436b86711a8ea7 /nmigen_boards/resources/memory.py | |
| parent | d42a55f9b3989e32b3867a796b36b0819636194e (diff) | |
[breaking-change] resources.memory: add missing inversion on SRAMResource(dm=).
The semantics should be that a high bit of data mask (UB#LB#) enables
the write to the corresponding byte.
Diffstat (limited to 'nmigen_boards/resources/memory.py')
| -rw-r--r-- | nmigen_boards/resources/memory.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py index b2be757..7f45cad 100644 --- a/nmigen_boards/resources/memory.py +++ b/nmigen_boards/resources/memory.py @@ -97,7 +97,7 @@ def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, io.append(Subsignal("a", Pins(a, dir="o", conn=conn))) io.append(Subsignal("d", Pins(d, dir="io", conn=conn))) if dm is not None: - io.append(Subsignal("dm", Pins(dm, dir="o", conn=conn))) # dm="LB# UB#" + io.append(Subsignal("dm", PinsN(dm, dir="o", conn=conn))) # dm="LB# UB#" if attrs is not None: io.append(attrs) return Resource.family(*args, default_name="sram", ios=io) |