[breaking-change] Add `_n` suffix to argument names of pins with fixed inverters.

Note: this change does NOT affect pin functionality or naming, and
does not require modifying your design. It does however affect some
board files, where keywords corresponding to active low pins will have
to be adjusted:
    SPIResource(0, cs="C1", ...) → SPIResource(0, cs_n="C1", ...)

The new naming scheme will make it easier to write and audit board
files by clearly marking inverted pins in resource factories, similarly to
how `PinsN` indicates the same in bare resources.

Fixes #129.

1 files changed, 30 insertions, 30 deletions

diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py
index 064369f..a363068 100644
--- a/nmigen_boards/resources/memory.py
+++ b/nmigen_boards/resources/memory.py
@@ -7,22 +7,22 @@ __all__ = [
 ]
 
 
-def SPIFlashResources(*args, cs, clk, copi, cipo, wp=None, hold=None,
+def SPIFlashResources(*args, cs_n, clk, copi, cipo, wp_n=None, hold_n=None,
                       conn=None, attrs=None):
     resources = []
 
     io_all = []
     if attrs is not None:
         io_all.append(attrs)
-    io_all.append(Subsignal("cs",  PinsN(cs, dir="o", conn=conn)))
+    io_all.append(Subsignal("cs",  PinsN(cs_n, dir="o", conn=conn)))
     io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
 
     io_1x = list(io_all)
     io_1x.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
     io_1x.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
-    if wp is not None and hold is not None:
-        io_1x.append(Subsignal("wp",   PinsN(wp,   dir="o", conn=conn, assert_width=1)))
-        io_1x.append(Subsignal("hold", PinsN(hold, dir="o", conn=conn, assert_width=1)))
+    if wp_n is not None and hold_n is not None:
+        io_1x.append(Subsignal("wp",   PinsN(wp_n,   dir="o", conn=conn, assert_width=1)))
+        io_1x.append(Subsignal("hold", PinsN(hold_n, dir="o", conn=conn, assert_width=1)))
     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
                                      name_suffix="1x"))
 
@@ -32,9 +32,9 @@ def SPIFlashResources(*args, cs, clk, copi, cipo, wp=None, hold=None,
     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
                                      name_suffix="2x"))
 
-    if wp is not None and hold is not None:
+    if wp_n is not None and hold_n is not None:
         io_4x = list(io_all)
-        io_4x.append(Subsignal("dq", Pins(" ".join([copi, cipo, wp, hold]), dir="io", conn=conn,
+        io_4x.append(Subsignal("dq", Pins(" ".join([copi, cipo, wp_n, hold_n]), dir="io", conn=conn,
                                           assert_width=4)))
         resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
                                          name_suffix="4x"))
@@ -42,7 +42,7 @@ def SPIFlashResources(*args, cs, clk, copi, cipo, wp=None, hold=None,
     return resources
 
 
-def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=None, wp=None,
+def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=None, wp_n=None,
                     conn=None, attrs=None):
     resources = []
 
@@ -51,8 +51,8 @@ def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=N
         io_common.append(attrs)
     if cd is not None:
         io_common.append(Subsignal("cd", Pins(cd, dir="i", conn=conn, assert_width=1)))
-    if wp is not None:
-        io_common.append(Subsignal("wp", PinsN(wp, dir="i", conn=conn, assert_width=1)))
+    if wp_n is not None:
+        io_common.append(Subsignal("wp", PinsN(wp_n, dir="i", conn=conn, assert_width=1)))
 
     io_native = list(io_common)
     io_native.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
@@ -86,34 +86,34 @@ def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=N
     return resources
 
 
-def SRAMResource(*args, cs, oe=None, we, a, d, dm=None,
+def SRAMResource(*args, cs_n, oe_n=None, we_n, a, d, dm_n=None,
                  conn=None, attrs=None):
     io = []
-    io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1)))
-    if oe is not None:
+    io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+    if oe_n is not None:
         # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
-        io.append(Subsignal("oe", PinsN(oe, dir="o", conn=conn, assert_width=1)))
-    io.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1)))
+        io.append(Subsignal("oe", PinsN(oe_n, dir="o", conn=conn, assert_width=1)))
+    io.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
     io.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
     io.append(Subsignal("d", Pins(d, dir="io", conn=conn)))
-    if dm is not None:
-        io.append(Subsignal("dm", PinsN(dm, dir="o", conn=conn))) # dm="LB# UB#"
+    if dm_n is not None:
+        io.append(Subsignal("dm", PinsN(dm_n, dir="o", conn=conn))) # dm="LB# UB#"
     if attrs is not None:
         io.append(attrs)
     return Resource.family(*args, default_name="sram", ios=io)
 
 
-def SDRAMResource(*args, clk, cke=None, cs=None, we, ras, cas, ba, a, dq, dqm=None,
+def SDRAMResource(*args, clk, cke=None, cs_n=None, we_n, ras_n, cas_n, ba, a, dq, dqm=None,
                   conn=None, attrs=None):
     io = []
     io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
     if cke is not None:
         io.append(Subsignal("clk_en", Pins(cke, dir="o", conn=conn, assert_width=1)))
-    if cs is not None:
-        io.append(Subsignal("cs",  PinsN(cs,  dir="o", conn=conn, assert_width=1)))
-    io.append(Subsignal("we",  PinsN(we,  dir="o", conn=conn, assert_width=1)))
-    io.append(Subsignal("ras", PinsN(ras, dir="o", conn=conn, assert_width=1)))
-    io.append(Subsignal("cas", PinsN(cas, dir="o", conn=conn, assert_width=1)))
+    if cs_n is not None:
+        io.append(Subsignal("cs", PinsN(cs_n,  dir="o", conn=conn, assert_width=1)))
+    io.append(Subsignal("we",  PinsN(we_n,  dir="o", conn=conn, assert_width=1)))
+    io.append(Subsignal("ras", PinsN(ras_n, dir="o", conn=conn, assert_width=1)))
+    io.append(Subsignal("cas", PinsN(cas_n, dir="o", conn=conn, assert_width=1)))
     io.append(Subsignal("ba", Pins(ba, dir="o", conn=conn)))
     io.append(Subsignal("a",  Pins(a,  dir="o", conn=conn)))
     io.append(Subsignal("dq", Pins(dq, dir="io", conn=conn)))
@@ -124,20 +124,20 @@ def SDRAMResource(*args, clk, cke=None, cs=None, we, ras, cas, ba, a, dq, dqm=No
     return Resource.family(*args, default_name="sdram", ios=io)
 
 
-def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq,
+def NORFlashResources(*args, rst=None, byte_n=None, cs_n, oe_n, we_n, wp_n, by, a, dq,
                       conn=None, attrs=None):
     resources = []
 
     io_common = []
     if rst is not None:
         io_common.append(Subsignal("rst", Pins(rst, dir="o", conn=conn, assert_width=1)))
-    io_common.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1)))
-    io_common.append(Subsignal("oe", PinsN(oe, dir="o", conn=conn, assert_width=1)))
-    io_common.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1)))
-    io_common.append(Subsignal("wp", PinsN(wp, dir="o", conn=conn, assert_width=1)))
+    io_common.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
+    io_common.append(Subsignal("oe", PinsN(oe_n, dir="o", conn=conn, assert_width=1)))
+    io_common.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
+    io_common.append(Subsignal("wp", PinsN(wp_n, dir="o", conn=conn, assert_width=1)))
     io_common.append(Subsignal("rdy", Pins(by, dir="i", conn=conn, assert_width=1)))
 
-    if byte is None:
+    if byte_n is None:
         io_8bit = list(io_common)
         io_8bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
         io_8bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=8)))
@@ -147,7 +147,7 @@ def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq,
         *dq_0_14, dq15_am1 = dq.split()
 
         # If present in a requested resource, this pin needs to be strapped correctly.
-        io_common.append(Subsignal("byte", PinsN(byte, dir="o", conn=conn, assert_width=1)))
+        io_common.append(Subsignal("byte", PinsN(byte_n, dir="o", conn=conn, assert_width=1)))
 
         io_8bit = list(io_common)
         io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o", conn=conn)))