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authorStaf Verhaegen <staf@stafverhaegen.be>2020-08-10 20:17:17 +0200
committerGitHub <noreply@github.com>2020-08-10 18:17:17 +0000
commit689a76207a61433b802ccdc96f5ffc3d07d81cec (patch)
tree7375f62537c4b3408f932f5144498a8433ff09f7 /nmigen_boards
parentf26a72913e9293ccb7f609a25ffa3bc0d33e0a79 (diff)
[breaking-change] Arty A7: rename cpu_reset resource to rst. (#102)
It's now define properly as input and used as default reset.
Diffstat (limited to 'nmigen_boards')
-rw-r--r--nmigen_boards/arty_a7.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/nmigen_boards/arty_a7.py b/nmigen_boards/arty_a7.py
index b1defe1..7e7e628 100644
--- a/nmigen_boards/arty_a7.py
+++ b/nmigen_boards/arty_a7.py
@@ -14,9 +14,11 @@ class ArtyA7Platform(Xilinx7SeriesPlatform):
package = "csg324"
speed = "1L"
default_clk = "clk100"
+ default_rst = "rst"
resources = [
Resource("clk100", 0, Pins("E3", dir="i"),
Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),
+ Resource("rst", 0, Pins("C2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
*LEDResources(pins="H5 J5 T9 T10", attrs=Attrs(IOSTANDARD="LVCMOS33")),
@@ -33,8 +35,6 @@ class ArtyA7Platform(Xilinx7SeriesPlatform):
attrs=Attrs(IOSTANDARD="LVCMOS33")
),
- Resource("cpu_reset", 0, Pins("C2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
-
SPIResource(0,
cs="C1", clk="F1", copi="H1", cipo="G1",
attrs=Attrs(IOSTANDARD="LVCMOS33")