diff options
| author | awygle <awygle@gmail.com> | 2020-11-04 22:52:12 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-11-05 06:52:12 +0000 |
| commit | ec65568d91dca4ca2ff7da22b90ad6574bbad68a (patch) | |
| tree | b99cf827aaf1edcfb34f3aae5228d3e81c0d916e /nmigen_boards | |
| parent | bcc14672994a3cdd04b7c0e1620d6f5e05145d94 (diff) | |
Factor out I2C resource.
Diffstat (limited to 'nmigen_boards')
| -rw-r--r-- | nmigen_boards/arty_s7.py | 7 | ||||
| -rw-r--r-- | nmigen_boards/genesys2.py | 6 | ||||
| -rw-r--r-- | nmigen_boards/resources/interface.py | 11 |
3 files changed, 15 insertions, 9 deletions
diff --git a/nmigen_boards/arty_s7.py b/nmigen_boards/arty_s7.py index 2871dae..633ba0a 100644 --- a/nmigen_boards/arty_s7.py +++ b/nmigen_boards/arty_s7.py @@ -38,10 +38,9 @@ class _ArtyS7Platform(Xilinx7SeriesPlatform): attrs=Attrs(IOSTANDARD="LVCMOS33") ), - Resource("i2c", 0, - Subsignal("scl", Pins("J14", dir="io")), - Subsignal("sda", Pins("J13", dir="io")), - Attrs(IOSTANDARD="LVCMOS33") + I2CResource(0, + scl="J14", sda="J13", + attrs=Attrs(IOSTANDARD="LVCMOS33") ), *SPIFlashResources(0, diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py index 40dbced..1c4ee54 100644 --- a/nmigen_boards/genesys2.py +++ b/nmigen_boards/genesys2.py @@ -52,10 +52,8 @@ class Genesys2Platform(Xilinx7SeriesPlatform): Attrs(IOSTANDARD="LVCMOS33")), UARTResource(0, rx="Y20", tx="Y23", attrs=Attrs(IOSTANDARD="LVCMOS33")), - Resource("i2c", 0, - Subsignal("scl", Pins("AE30", dir="io")), - Subsignal("sda", Pins("AF30", dir="io")), - Attrs(IOSTANDARD="LVCMOS33")), + I2CResource(0, scl="AE30", sda="AF30", + attrs=Attrs(IOSTANDARD="LVCMOS33")), Resource("ddr3", 0, Subsignal("rst", PinsN("AG5", dir="o"), Attrs(IOSTANDARD="SSTL15")), diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py index 7244062..9710ffb 100644 --- a/nmigen_boards/resources/interface.py +++ b/nmigen_boards/resources/interface.py @@ -2,7 +2,7 @@ from nmigen.build import * __all__ = [ - "UARTResource", "IrDAResource", "SPIResource", + "UARTResource", "IrDAResource", "SPIResource", "I2CResource", "DirectUSBResource", "ULPIResource" ] @@ -86,6 +86,15 @@ def SPIResource(*args, cs, clk, copi, cipo, int=None, reset=None, return Resource.family(*args, default_name="spi", ios=io) +def I2CResource(*args, scl, sda, conn=None, attrs=None): + io = [] + io.append(Subsignal("scl", Pins(scl, dir="io", conn=conn, assert_width=1))) + io.append(Subsignal("sda", Pins(sda, dir="io", conn=conn, assert_width=1))) + if attrs is not None: + io.append(attrs) + return Resource.family(*args, default_name="i2c", ios=io) + + def DirectUSBResource(*args, d_p, d_n, pullup=None, vbus_valid=None, conn=None, attrs=None): |