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-rw-r--r--nmigen_boards/genesys2.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py
index 66525fd..b23976f 100644
--- a/nmigen_boards/genesys2.py
+++ b/nmigen_boards/genesys2.py
@@ -99,8 +99,8 @@ class Genesys2Platform(Xilinx7SeriesPlatform):
Resource("audio_clk", 0, # ADAU1761 MCLK
Pins("AK19", dir="o"), Attrs(IOSTANDARD="LVCMOS18")),
SPIResource(0, # OLED, SSD1306, 128 x 32
- cs="dummy-cs0", clk="AF17", mosi="Y15",
- miso="dummy-miso0", reset="AB17",
+ cs="dummy-cs0", clk="AF17", copi="Y15",
+ cipo="dummy-cipo0", reset="AB17",
attrs=Attrs(IOSTANDARD="LVCMOS18")),
Resource("oled", 0, # OLED, UG-2832HSWEG04
Subsignal("dc", Pins("AC17", dir="o")),