| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-07-13 | orangecrab_r0_2: IO_STANDARD -> IO_TYPE | Gwenhael Goavec-Merou | |
| 2020-07-13 | Add OrangeCrab R2.0 board. | Thomas Daede | |
| 2020-07-13 | Add RGB LEDs to blinky test. | Thomas Daede | |
| 2020-07-09 | Add ECPIX-5 support. | Jean-François Nguyen | |
| 2020-07-08 | kcu105: merge temperature grade into speed grade. | whitequark | |
| 2020-07-04 | de0_cv: fix ba and cs pins of the SDRAM resource. | Andrew Clark | |
| 2020-07-02 | [breaking-change] resources.memory: add missing inversion on SRAMResource(dm=). | whitequark | |
| The semantics should be that a high bit of data mask (UB#LB#) enables the write to the corresponding byte. | |||
| 2020-06-28 | ecp5_evn: add SPI Flash, UART, and EXTCLK peripherals | Aled Cuda | |
| 2020-06-27 | de0_cv: remove SD card WP pin (not present on this board). | whitequark | |
| 2020-06-22 | resources: allow UARTResource without control signals to have no role. | whitequark | |
| 2020-06-22 | {machXO3_sk→machxo3_sk}: follow naming conventions | whitequark | |
| 2020-06-22 | machXO3_sk: fix platform name | Gwenhael Goavec-Merou | |
| Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com> | |||
| 2020-06-21 | Add Lattice MachXO3LF Starter Kit | Gwenhael Goavec-Merou | |
| 2020-06-21 | tinyfpga_axN: use lattice_machxo_2_3l instead of lattice_machxo2 | Gwenhael Goavec-Merou | |
| 2020-06-11 | icestick: fix UART flow control pins. | Ivan Grokhotkov | |
| UART flow control pins match the signal names in the schematic, but directions are reversed. Fix by setting role=dce. | |||
| 2020-06-11 | [breaking-change] ice40_hx8k_b_evn: fix UART flow control pins. | Ivan Grokhotkov | |
| RTS/CTS and DTR/DSR pairs have been swapped to work around the signal direction in UARTResource. Un-reverse the signals, making the names match the schematic. Fix the direction by setting role=dce. Ref. http://www.latticesemi.com/view_document?document_id=50373 | |||
| 2020-06-11 | de0: fix UART RTS/CTS direction. | Ivan Grokhotkov | |
| RTS and CTS match the schematic, but the direction is incorrect: CTS is output, RTS is input. Fix by setting role=dce. Ref. https://www.intel.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-5804152209-de0-user-manual.pdf | |||
| 2020-06-11 | [breaking-change] nexys4ddr: fix UART RTS/CTS pins. | Ivan Grokhotkov | |
| According to the schematic, RTS is E5 and CTS is D3. Previously these were reversed to work around signal direction set in UARTResource. Un-reverse the signals, and set correct direction by passing role=dce. Ref. https://reference.digilentinc.com/_media/nexys4-ddr:nexys_4_ddr_sch.pdf | |||
| 2020-06-11 | [breaking-change] blackice: remove UART RTS/CTS signals. | Ivan Grokhotkov | |
| According to the schematic, RTS and CTS are not connected to CH340G in this version of the board. Ref. https://github.com/monsonite/BackIce_FPGA/blob/master/BlackIce18_07_01D.pdf and https://forum.mystorm.uk/uploads/default/original/1X/a5db1ce1c9bc2d91e63cfdc8424d699c2419a3d0.png | |||
| 2020-06-11 | blackice_ii: fix UART RTS/CTS direction. | Ivan Grokhotkov | |
| Pin numbers match the P0/P1 signals in the schematic, but the direction is reversed. Fix by setting role="dce". Ref. https://github.com/mystorm-org/BlackIce-II/blob/master/hardware/BlackIce.pdf | |||
| 2020-06-11 | [breaking-change] resources: distinguish "dte"/"dce" roles of UART. | Ivan Grokhotkov | |
| UARTResource gets a new argument, "role", which determines flow control signal directions: - DCE means that the design acts as a modem - DTE means that the design acts as a PC | |||
| 2020-05-28 | Add Digilent Genesys2 board. | Alain Péteut | |
| 2020-05-08 | tinyfpga_ax{1,2}: add missing `resources`. | Simon Kirkby | |
| 2020-04-24 | Add ICE40UP5K-B-EVN. | WRansohoff | |
| 2020-04-13 | ecp5_5g_evn: add connectors. | x44203 | |
| 2020-03-23 | Add Upduino v1/v2. | WRansohoff | |
| 2020-03-20 | ecp5_5g_evn: add variable IO standards and SERDES resources. | x44203 | |
| 2020-03-19 | zturn_lite: fix typo | Robin Ole Heinemann | |
| 2020-03-17 | nexys4ddr: enable pushbutton reset. | Stuart Olsen | |
| 2020-03-14 | resources.display: Apply inversion setting to dp | Stuart Olsen | |
| 2020-03-12 | Ad DE10-Lite. | Yusuf Taiwo Hassan | |
| 2020-02-10 | Add Alchitry Au board definition. | Joshua Koike | |
| 2020-02-06 | versa_ecp5: fix switch{4..7} IO_TYPE. | whitequark | |
| 2020-02-03 | Add Fomu PVT support. | Jean THOMAS | |
| 2020-01-18 | artyz7: fix attribute name. | Nicolas Robin | |
| 2020-01-17 | Add Digilent Arty Z7-20 board. | Nicolas Robin | |
| 2020-01-15 | Add Digilent Nexys 4 DDR board. | Nicolas Robin | |
| 2020-01-13 | blinky: replace deprecated Signal(max=...) (#42) | Nicolas Robin | |
| 2020-01-12 | ice40_hx8k_b_evn: fix swapped DTR/DSR | Nicolas Robin | |
| 2020-01-12 | ice40_hx8k_b_evn: fix swapped RTS/CTS | Nicolas Robin | |
| 2019-12-31 | Add Lattice ECP5-5G Evaluation Board stub. | whitequark | |
| 2019-11-30 | mister: fix SD card typo | Dan Ravensloft | |
| 2019-11-28 | tinyfpga_bx: fix definition of io pin 17 | Ezekiel Bethel | |
| 2019-10-25 | [breaking-change] Atlys: use reset button as reset | Staf Verhaegen | |
| 2019-10-25 | Add DE10-Nano-based MiSTer. | Dan Ravensloft | |
| 2019-10-13 | resources.memory: fix typo. | whitequark | |
| 2019-10-11 | [breaking-change] icebreaker: update leftover user_* resources. | whitequark | |
| 2019-10-11 | [breaking-change] mercury: update leftover user_btn resources. | whitequark | |
| 2019-10-11 | resources: add conn= argument to every factory. | whitequark | |
| 2019-10-10 | Add KCU105 board stub. | whitequark | |
 |
index : amaranth-boards | |
| Board definitions for Amaranth HDL |
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path: root/nmigen_boards