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AgeCommit message (Collapse)Author
2020-08-06Add Hackaday Supercon19Badge.Katherine Temkin
2020-08-05Add MicroZed Z010 and Z020.Robin Heinemann
2020-08-03ecpix5: add termination attributes to DDR3 signalsJean THOMAS
2020-07-28Add iCEBreaker Bitsy.Kate Temkin
2020-07-27Add ULX3S.Kate Temkin
2020-07-27orangecrab_r0_2: fix sense diffpair.Joshua Koike
2020-07-27orangecrab_r0_2: convert sense to diffpairJoshua Koike
2020-07-22tinyfpga_axN: use vendor.lattice_machxo2, not .lattice_machxo_2_3l.whitequark
This restores compatibility with nMigen 0.2.
2020-07-21fomu_pvt: fix typoRobin Ole Heinemann
2020-07-19Factor out direct USB and ULPI resources.Kate Temkin
2020-07-18mercury: fix SPI rolesRobin Ole Heinemann
2020-07-16ecpix5: fix PMOD4 pins.Jean-François Nguyen
2020-07-16[breaking-change] Update SPI pin names.ECP5-PCIe
The new names follow the OSHWA convention described at: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
2020-07-15Add OrangeCrab r0.1Mike Walters
2020-07-14orangecrab_r0_2: fix dq pin definitions.Mike Walters
2020-07-13orangecrab_r0_2: IO_STANDARD -> IO_TYPEGwenhael Goavec-Merou
2020-07-13Add OrangeCrab R2.0 board.Thomas Daede
2020-07-13Add RGB LEDs to blinky test.Thomas Daede
2020-07-09Add ECPIX-5 support.Jean-François Nguyen
2020-07-08kcu105: merge temperature grade into speed grade.whitequark
2020-07-04de0_cv: fix ba and cs pins of the SDRAM resource.Andrew Clark
2020-07-02[breaking-change] resources.memory: add missing inversion on SRAMResource(dm=).whitequark
The semantics should be that a high bit of data mask (UB#LB#) enables the write to the corresponding byte.
2020-06-28ecp5_evn: add SPI Flash, UART, and EXTCLK peripheralsAled Cuda
2020-06-27de0_cv: remove SD card WP pin (not present on this board).whitequark
2020-06-22resources: allow UARTResource without control signals to have no role.whitequark
2020-06-22{machXO3_sk→machxo3_sk}: follow naming conventionswhitequark
2020-06-22machXO3_sk: fix platform nameGwenhael Goavec-Merou
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2020-06-21Add Lattice MachXO3LF Starter KitGwenhael Goavec-Merou
2020-06-21tinyfpga_axN: use lattice_machxo_2_3l instead of lattice_machxo2Gwenhael Goavec-Merou
2020-06-11icestick: fix UART flow control pins.Ivan Grokhotkov
UART flow control pins match the signal names in the schematic, but directions are reversed. Fix by setting role=dce.
2020-06-11[breaking-change] ice40_hx8k_b_evn: fix UART flow control pins.Ivan Grokhotkov
RTS/CTS and DTR/DSR pairs have been swapped to work around the signal direction in UARTResource. Un-reverse the signals, making the names match the schematic. Fix the direction by setting role=dce. Ref. http://www.latticesemi.com/view_document?document_id=50373
2020-06-11de0: fix UART RTS/CTS direction.Ivan Grokhotkov
RTS and CTS match the schematic, but the direction is incorrect: CTS is output, RTS is input. Fix by setting role=dce. Ref. https://www.intel.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-5804152209-de0-user-manual.pdf
2020-06-11[breaking-change] nexys4ddr: fix UART RTS/CTS pins.Ivan Grokhotkov
According to the schematic, RTS is E5 and CTS is D3. Previously these were reversed to work around signal direction set in UARTResource. Un-reverse the signals, and set correct direction by passing role=dce. Ref. https://reference.digilentinc.com/_media/nexys4-ddr:nexys_4_ddr_sch.pdf
2020-06-11[breaking-change] blackice: remove UART RTS/CTS signals.Ivan Grokhotkov
According to the schematic, RTS and CTS are not connected to CH340G in this version of the board. Ref. https://github.com/monsonite/BackIce_FPGA/blob/master/BlackIce18_07_01D.pdf and https://forum.mystorm.uk/uploads/default/original/1X/a5db1ce1c9bc2d91e63cfdc8424d699c2419a3d0.png
2020-06-11blackice_ii: fix UART RTS/CTS direction.Ivan Grokhotkov
Pin numbers match the P0/P1 signals in the schematic, but the direction is reversed. Fix by setting role="dce". Ref. https://github.com/mystorm-org/BlackIce-II/blob/master/hardware/BlackIce.pdf
2020-06-11[breaking-change] resources: distinguish "dte"/"dce" roles of UART.Ivan Grokhotkov
UARTResource gets a new argument, "role", which determines flow control signal directions: - DCE means that the design acts as a modem - DTE means that the design acts as a PC
2020-05-28Add Digilent Genesys2 board.Alain Péteut
2020-05-08tinyfpga_ax{1,2}: add missing `resources`.Simon Kirkby
2020-04-24Add ICE40UP5K-B-EVN.WRansohoff
2020-04-13ecp5_5g_evn: add connectors.x44203
2020-03-23Add Upduino v1/v2.WRansohoff
2020-03-20ecp5_5g_evn: add variable IO standards and SERDES resources.x44203
2020-03-19zturn_lite: fix typoRobin Ole Heinemann
2020-03-17nexys4ddr: enable pushbutton reset.Stuart Olsen
2020-03-14resources.display: Apply inversion setting to dpStuart Olsen
2020-03-12Ad DE10-Lite.Yusuf Taiwo Hassan
2020-02-10Add Alchitry Au board definition.Joshua Koike
2020-02-06versa_ecp5: fix switch{4..7} IO_TYPE.whitequark
2020-02-03Add Fomu PVT support.Jean THOMAS
2020-01-18artyz7: fix attribute name.Nicolas Robin
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