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| author | Miodrag Milanovic <mmicko@gmail.com> | 2024-12-11 13:06:06 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2024-12-11 13:06:06 +0100 |
| commit | afb459ae2acc6b969dc5fcae3431f59ae134f8fa (patch) | |
| tree | 4ba160c75cedb609531ba63457b53fb60adbe3b0 /docs/source/io_tile.rst | |
| parent | 789a46da5edc03dac287d97a7bc173a3f5de89e6 (diff) | |
Fix some of docs table layouts
Diffstat (limited to 'docs/source/io_tile.rst')
| -rw-r--r-- | docs/source/io_tile.rst | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/docs/source/io_tile.rst b/docs/source/io_tile.rst index 12d09b6..1ed707b 100644 --- a/docs/source/io_tile.rst +++ b/docs/source/io_tile.rst @@ -327,11 +327,17 @@ configured as follows (bits listed from LSB to MSB): | | | Parameter | +=======================+=======================+=======================+ | 0 3 | PLLCONFIG_5 | Select PLL Type: | +| | +-----------------------+ | | | 000 = DISABLED | +| | +-----------------------+ | | | 010 = SB_PLL40_PAD | +| | +-----------------------+ | | | 100 = SB_PLL40_2_PAD | +| | +-----------------------+ | | | 110 = SB_PLL40_2F_PAD | +| | +-----------------------+ | | | 011 = SB_PLL40_CORE | +| | +-----------------------+ | | | 111 = | | | | SB_PLL40_2F_CORE | +-----------------------+-----------------------+-----------------------+ @@ -340,10 +346,14 @@ configured as follows (bits listed from LSB to MSB): | 0 5 | PLLCONFIG_3 | | +-----------------------+-----------------------+-----------------------+ | 0 5 | PLLCONFIG_5 | FEEDBACK_PATH | +| | +-----------------------+ | | | 000 = "DELAY" | +| | +-----------------------+ | | | 001 = "SIMPLE" | +| | +-----------------------+ | | | 010 = | | | | "PHASE_AND_DELAY" | +| | +-----------------------+ | | | 110 = "EXTERNAL" | +-----------------------+-----------------------+-----------------------+ | 0 2 | PLLCONFIG_9 | | @@ -352,27 +362,39 @@ configured as follows (bits listed from LSB to MSB): +-----------------------+-----------------------+-----------------------+ | 0 4 | PLLCONFIG_4 | DELAY_ADJ | | | | USTMENT_MODE_FEEDBACK | +| | +-----------------------+ | | | 0 = "FIXED" | +| | +-----------------------+ | | | 1 = "DYNAMIC" | +-----------------------+-----------------------+-----------------------+ | 0 4 | PLLCONFIG_9 | DELAY_ADJ | | | | USTMENT_MODE_RELATIVE | +| | +-----------------------+ | | | 0 = "FIXED" | +| | +-----------------------+ | | | 1 = "DYNAMIC" | +-----------------------+-----------------------+-----------------------+ | 0 3 | PLLCONFIG_6 | PLLOUT_SELECT | | | | PLLOUT_SELECT_PORTA | +| | +-----------------------+ | | | 00 = "GENCLK" | +| | +-----------------------+ | | | 01 = "GENCLK_HALF" | +| | +-----------------------+ | | | 10 = "SHIFTREG_90deg" | +| | +-----------------------+ | | | 11 = "SHIFTREG_0deg" | +-----------------------+-----------------------+-----------------------+ | 0 3 | PLLCONFIG_7 | | +-----------------------+-----------------------+-----------------------+ | 0 3 | PLLCONFIG_2 | PLLOUT_SELECT_PORTB | +| | +-----------------------+ | | | 00 = "GENCLK" | +| | +-----------------------+ | | | 01 = "GENCLK_HALF" | +| | +-----------------------+ | | | 10 = "SHIFTREG_90deg" | +| | +-----------------------+ | | | 11 = "SHIFTREG_0deg" | +-----------------------+-----------------------+-----------------------+ | 0 3 | PLLCONFIG_3 | | |