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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-18 18:37:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-18 18:38:01 +0200 |
| commit | 70e01c1802bef592452cada1cba0224185e8029e (patch) | |
| tree | e07e7ea93c566e754d2e69768b094da126c7e1e7 /examples/icestick/Makefile | |
| parent | 50915bf151e57fd1881dc19293e20301b01750f8 (diff) | |
Add pre- and post-synthesis testbench examples
Diffstat (limited to 'examples/icestick/Makefile')
| -rw-r--r-- | examples/icestick/Makefile | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile index 9294608..d687d14 100644 --- a/examples/icestick/Makefile +++ b/examples/icestick/Makefile @@ -18,6 +18,21 @@ all: $(PROJ).rpt $(PROJ).bin %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< +%_tb: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb + ./$< +vcd=$@ + +%_syn.v: %.blif + yosys -o $@ $^ + +%_syntb: %_tb.v %_syn.v + iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + +%_syntb.vcd: %_syntb + ./$< +vcd=$@ + prog: $(PROJ).bin iceprog $< |