First commit

3 files changed, 1070 insertions, 0 deletions

diff --git a/chips/imxrt1060/src/iomuxc.rs b/chips/imxrt1060/src/iomuxc.rs
new file mode 100644
index 0000000..60272ea
--- /dev/null
+++ b/chips/imxrt1060/src/iomuxc.rs
@@ -0,0 +1,287 @@
+//! I/O multiplexing and configuration.
+
+pub type RegisterBlock = imxrt_drivers_iomuxc_10xx::iomuxc::RegisterBlock<20, 124, 231>;
+
+pub use imxrt_drivers_iomuxc_10xx::iomuxc::{SELECT_INPUT, SW_MUX_CTL_PAD, SW_PAD_CTL_PAD};
+
+/// Indices for `sw_[pad|mux]_ctl_pad` registers.
+pub mod pad {
+    pub const GPIO_EMC_00: usize = 0;
+    pub const GPIO_EMC_01: usize = 1;
+    pub const GPIO_EMC_02: usize = 2;
+    pub const GPIO_EMC_03: usize = 3;
+    pub const GPIO_EMC_04: usize = 4;
+    pub const GPIO_EMC_05: usize = 5;
+    pub const GPIO_EMC_06: usize = 6;
+    pub const GPIO_EMC_07: usize = 7;
+    pub const GPIO_EMC_08: usize = 8;
+    pub const GPIO_EMC_09: usize = 9;
+    pub const GPIO_EMC_10: usize = 10;
+    pub const GPIO_EMC_11: usize = 11;
+    pub const GPIO_EMC_12: usize = 12;
+    pub const GPIO_EMC_13: usize = 13;
+    pub const GPIO_EMC_14: usize = 14;
+    pub const GPIO_EMC_15: usize = 15;
+    pub const GPIO_EMC_16: usize = 16;
+    pub const GPIO_EMC_17: usize = 17;
+    pub const GPIO_EMC_18: usize = 18;
+    pub const GPIO_EMC_19: usize = 19;
+    pub const GPIO_EMC_20: usize = 20;
+    pub const GPIO_EMC_21: usize = 21;
+    pub const GPIO_EMC_22: usize = 22;
+    pub const GPIO_EMC_23: usize = 23;
+    pub const GPIO_EMC_24: usize = 24;
+    pub const GPIO_EMC_25: usize = 25;
+    pub const GPIO_EMC_26: usize = 26;
+    pub const GPIO_EMC_27: usize = 27;
+    pub const GPIO_EMC_28: usize = 28;
+    pub const GPIO_EMC_29: usize = 29;
+    pub const GPIO_EMC_30: usize = 30;
+    pub const GPIO_EMC_31: usize = 31;
+    pub const GPIO_EMC_32: usize = 32;
+    pub const GPIO_EMC_33: usize = 33;
+    pub const GPIO_EMC_34: usize = 34;
+    pub const GPIO_EMC_35: usize = 35;
+    pub const GPIO_EMC_36: usize = 36;
+    pub const GPIO_EMC_37: usize = 37;
+    pub const GPIO_EMC_38: usize = 38;
+    pub const GPIO_EMC_39: usize = 39;
+    pub const GPIO_EMC_40: usize = 40;
+    pub const GPIO_EMC_41: usize = 41;
+    pub const GPIO_AD_B0_04: usize = 46;
+    pub const GPIO_AD_B0_05: usize = 47;
+    pub const GPIO_AD_B0_06: usize = 48;
+    pub const GPIO_AD_B0_07: usize = 49;
+    pub const GPIO_AD_B0_08: usize = 50;
+    pub const GPIO_AD_B0_09: usize = 51;
+    pub const GPIO_AD_B0_10: usize = 52;
+    pub const GPIO_AD_B0_11: usize = 53;
+    pub const GPIO_AD_B0_12: usize = 54;
+    pub const GPIO_AD_B0_13: usize = 55;
+    pub const GPIO_AD_B0_14: usize = 56;
+    pub const GPIO_AD_B0_15: usize = 57;
+    pub const GPIO_AD_B1_00: usize = 58;
+    pub const GPIO_AD_B1_01: usize = 59;
+    pub const GPIO_AD_B1_02: usize = 60;
+    pub const GPIO_AD_B1_03: usize = 61;
+    pub const GPIO_AD_B1_04: usize = 62;
+    pub const GPIO_AD_B1_05: usize = 63;
+    pub const GPIO_AD_B1_06: usize = 64;
+    pub const GPIO_AD_B1_07: usize = 65;
+    pub const GPIO_B0_00: usize = 74;
+    pub const GPIO_B0_01: usize = 75;
+    pub const GPIO_B0_02: usize = 76;
+    pub const GPIO_B0_03: usize = 77;
+    pub const GPIO_B0_04: usize = 78;
+    pub const GPIO_B0_05: usize = 79;
+    pub const GPIO_B0_06: usize = 80;
+    pub const GPIO_B0_07: usize = 81;
+    pub const GPIO_B0_08: usize = 82;
+    pub const GPIO_B0_09: usize = 83;
+    pub const GPIO_B0_10: usize = 84;
+    pub const GPIO_B0_11: usize = 85;
+    pub const GPIO_B0_12: usize = 86;
+    pub const GPIO_B0_13: usize = 87;
+    pub const GPIO_B0_14: usize = 88;
+    pub const GPIO_B0_15: usize = 89;
+    pub const GPIO_B1_00: usize = 90;
+    pub const GPIO_B1_01: usize = 91;
+    pub const GPIO_B1_02: usize = 92;
+    pub const GPIO_B1_03: usize = 93;
+    pub const GPIO_B1_04: usize = 94;
+    pub const GPIO_B1_05: usize = 95;
+    pub const GPIO_B1_06: usize = 96;
+    pub const GPIO_B1_07: usize = 97;
+    pub const GPIO_B1_08: usize = 98;
+    pub const GPIO_B1_09: usize = 99;
+    pub const GPIO_B1_10: usize = 100;
+    pub const GPIO_B1_11: usize = 101;
+    pub const GPIO_B1_12: usize = 102;
+    pub const GPIO_B1_13: usize = 103;
+    pub const GPIO_B1_14: usize = 104;
+    pub const GPIO_B1_15: usize = 105;
+    pub const GPIO_SD_B0_00: usize = 106;
+    pub const GPIO_SD_B0_01: usize = 107;
+    pub const GPIO_SD_B0_02: usize = 108;
+    pub const GPIO_SD_B0_03: usize = 109;
+    pub const GPIO_SD_B0_04: usize = 110;
+    pub const GPIO_SD_B0_05: usize = 111;
+    pub const GPIO_SD_B1_00: usize = 112;
+    pub const GPIO_SD_B1_01: usize = 113;
+    pub const GPIO_SD_B1_02: usize = 114;
+    pub const GPIO_SD_B1_03: usize = 115;
+    pub const GPIO_SD_B1_04: usize = 116;
+    pub const GPIO_SD_B1_05: usize = 117;
+    pub const GPIO_SD_B1_06: usize = 118;
+    pub const GPIO_SD_B1_07: usize = 119;
+    pub const GPIO_SD_B1_08: usize = 120;
+    pub const GPIO_SD_B1_09: usize = 121;
+    pub const GPIO_SD_B1_10: usize = 122;
+    pub const GPIO_SD_B1_11: usize = 123;
+}
+
+/// Indices for `select_input` registers.
+pub mod select_input {
+    pub const ANATOP_USB_OTG1_ID: usize = 0;
+    pub const CCM_PMIC_READY: usize = 2;
+    pub const ENET_IPG_CLK_RMII: usize = 14;
+    pub const ENET_MDIO: usize = 15;
+    pub const ENET0_RXDATA: usize = 16;
+    pub const ENET1_RXDATA: usize = 17;
+    pub const ENET_RXEN: usize = 18;
+    pub const ENET_RXERR: usize = 19;
+    pub const ENET0_TIMER: usize = 20;
+    pub const ENET_TXCLK: usize = 21;
+    pub const FLEXCAN1_RX: usize = 22;
+    pub const FLEXCAN2_RX: usize = 23;
+    pub const FLEXPWM1_PWMA3: usize = 24;
+    pub const FLEXPWM1_PWMA0: usize = 25;
+    pub const FLEXPWM1_PWMA1: usize = 26;
+    pub const FLEXPWM1_PWMA2: usize = 27;
+    pub const FLEXPWM1_PWMB3: usize = 28;
+    pub const FLEXPWM1_PWMB0: usize = 29;
+    pub const FLEXPWM1_PWMB1: usize = 30;
+    pub const FLEXPWM1_PWMB2: usize = 31;
+    pub const FLEXPWM2_PWMA3: usize = 32;
+    pub const FLEXPWM2_PWMA0: usize = 33;
+    pub const FLEXPWM2_PWMA1: usize = 34;
+    pub const FLEXPWM2_PWMA2: usize = 35;
+    pub const FLEXPWM2_PWMB3: usize = 36;
+    pub const FLEXPWM2_PWMB0: usize = 37;
+    pub const FLEXPWM2_PWMB1: usize = 38;
+    pub const FLEXPWM2_PWMB2: usize = 39;
+    pub const FLEXPWM4_PWMA0: usize = 40;
+    pub const FLEXPWM4_PWMA1: usize = 41;
+    pub const FLEXPWM4_PWMA2: usize = 42;
+    pub const FLEXPWM4_PWMA3: usize = 43;
+    pub const FLEXSPIA_DQS: usize = 44;
+    pub const FLEXSPIA_DATA0: usize = 45;
+    pub const FLEXSPIA_DATA1: usize = 46;
+    pub const FLEXSPIA_DATA2: usize = 47;
+    pub const FLEXSPIA_DATA3: usize = 48;
+    pub const FLEXSPIB_DATA0: usize = 49;
+    pub const FLEXSPIB_DATA1: usize = 50;
+    pub const FLEXSPIB_DATA2: usize = 51;
+    pub const FLEXSPIB_DATA3: usize = 52;
+    pub const FLEXSPIA_SCK: usize = 53;
+    pub const LPI2C1_SCL: usize = 54;
+    pub const LPI2C1_SDA: usize = 55;
+    pub const LPI2C2_SCL: usize = 56;
+    pub const LPI2C2_SDA: usize = 57;
+    pub const LPI2C3_SCL: usize = 58;
+    pub const LPI2C3_SDA: usize = 59;
+    pub const LPI2C4_SCL: usize = 60;
+    pub const LPI2C4_SDA: usize = 61;
+    pub const LPSPI1_PCS0: usize = 62;
+    pub const LPSPI1_SCK: usize = 63;
+    pub const LPSPI1_SDI: usize = 64;
+    pub const LPSPI1_SDO: usize = 65;
+    pub const LPSPI2_PCS0: usize = 66;
+    pub const LPSPI2_SCK: usize = 67;
+    pub const LPSPI2_SDI: usize = 68;
+    pub const LPSPI2_SDO: usize = 69;
+    pub const LPSPI3_PCS0: usize = 74;
+    pub const LPSPI3_SCK: usize = 75;
+    pub const LPSPI3_SDI: usize = 76;
+    pub const LPSPI3_SDO: usize = 77;
+    pub const LPUART2_RX: usize = 78;
+    pub const LPUART2_TX: usize = 79;
+    pub const LPUART3_CTS_B: usize = 80;
+    pub const LPUART3_RX: usize = 81;
+    pub const LPUART3_TX: usize = 82;
+    pub const LPUART4_RX: usize = 83;
+    pub const LPUART4_TX: usize = 84;
+    pub const LPUART5_RX: usize = 85;
+    pub const LPUART5_TX: usize = 86;
+    pub const LPUART6_RX: usize = 87;
+    pub const LPUART6_TX: usize = 88;
+    pub const LPUART7_RX: usize = 89;
+    pub const LPUART7_TX: usize = 90;
+    pub const LPUART8_RX: usize = 91;
+    pub const LPUART8_TX: usize = 92;
+    pub const NMI: usize = 93;
+    pub const QTIMER2_TIMER0: usize = 94;
+    pub const QTIMER2_TIMER1: usize = 95;
+    pub const QTIMER2_TIMER2: usize = 96;
+    pub const QTIMER2_TIMER3: usize = 97;
+    pub const QTIMER3_TIMER0: usize = 98;
+    pub const QTIMER3_TIMER1: usize = 99;
+    pub const QTIMER3_TIMER2: usize = 100;
+    pub const QTIMER3_TIMER3: usize = 101;
+    pub const SAI1_MCLK2: usize = 102;
+    pub const SAI1_RX_BCLK: usize = 103;
+    pub const SAI1_RX_DATA0: usize = 104;
+    pub const SAI1_RX_DATA1: usize = 105;
+    pub const SAI1_RX_DATA2: usize = 106;
+    pub const SAI1_RX_DATA3: usize = 107;
+    pub const SAI1_RX_SYNC: usize = 108;
+    pub const SAI1_TX_BCLK: usize = 109;
+    pub const SAI1_TX_SYNC: usize = 110;
+    pub const SAI2_MCLK2: usize = 111;
+    pub const SAI2_RX_BCLK: usize = 112;
+    pub const SAI2_RX_DATA0: usize = 113;
+    pub const SAI2_RX_SYNC: usize = 114;
+    pub const SAI2_TX_BCLK: usize = 115;
+    pub const SAI2_TX_SYNC: usize = 116;
+    pub const SPDIF_IN: usize = 117;
+    pub const USB_OTG1_OC: usize = 119;
+    pub const USDHC1_CD_B: usize = 120;
+    pub const USDHC1_WP: usize = 121;
+    pub const USDHC2_CLK: usize = 122;
+    pub const USDHC2_CD_B: usize = 123;
+    pub const USDHC2_CMD: usize = 124;
+    pub const USDHC2_DATA0: usize = 125;
+    pub const USDHC2_DATA1: usize = 126;
+    pub const USDHC2_DATA2: usize = 127;
+    pub const USDHC2_DATA3: usize = 128;
+    pub const USDHC2_DATA4: usize = 129;
+    pub const USDHC2_DATA5: usize = 130;
+    pub const USDHC2_DATA6: usize = 131;
+    pub const USDHC2_DATA7: usize = 132;
+    pub const USDHC2_WP: usize = 133;
+    pub const XBAR1_IN02: usize = 134;
+    pub const XBAR1_IN03: usize = 135;
+    pub const XBAR1_IN04: usize = 136;
+    pub const XBAR1_IN05: usize = 137;
+    pub const XBAR1_IN06: usize = 138;
+    pub const XBAR1_IN07: usize = 139;
+    pub const XBAR1_IN08: usize = 140;
+    pub const XBAR1_IN09: usize = 141;
+    pub const XBAR1_IN17: usize = 142;
+    pub const XBAR1_IN18: usize = 143;
+    pub const XBAR1_IN20: usize = 144;
+    pub const XBAR1_IN22: usize = 145;
+    pub const XBAR1_IN23: usize = 146;
+    pub const XBAR1_IN24: usize = 147;
+    pub const XBAR1_IN14: usize = 148;
+    pub const XBAR1_IN15: usize = 149;
+    pub const XBAR1_IN16: usize = 150;
+    pub const XBAR1_IN25: usize = 151;
+    pub const XBAR1_IN19: usize = 152;
+    pub const XBAR1_IN21: usize = 153;
+    pub const FLEXSPI2_IPP_IND_DQS_FA: usize = 206;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT0: usize = 207;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT1: usize = 208;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT2: usize = 209;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT3: usize = 210;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT0: usize = 211;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT1: usize = 212;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT2: usize = 213;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT3: usize = 214;
+    pub const FLEXSPI2_IPP_IND_SCK_FA: usize = 215;
+    pub const FLEXSPI2_IPP_IND_SCK_FB: usize = 216;
+    pub const GPT1_IPP_IND_CAPIN1: usize = 217;
+    pub const GPT1_IPP_IND_CAPIN2: usize = 218;
+    pub const GPT1_IPP_IND_CLKIN: usize = 219;
+    pub const GPT2_IPP_IND_CAPIN1: usize = 220;
+    pub const GPT2_IPP_IND_CAPIN2: usize = 221;
+    pub const GPT2_IPP_IND_CLKIN: usize = 222;
+    pub const SAI3_IPG_CLK_SAI_MCLK_S: usize = 223;
+    pub const SAI3_IPP_IND_SAI_RXBCLK: usize = 224;
+    pub const SAI3_IPP_IND_SAI_RXDATA_S: usize = 225;
+    pub const SAI3_IPP_IND_SAI_RXSYNC: usize = 226;
+    pub const SAI3_IPP_IND_SAI_TXBCLK: usize = 227;
+    pub const SAI3_IPP_IND_SAI_TXSYNC: usize = 228;
+    pub const SEMC_I_IPP_IND_DQS4: usize = 229;
+    pub const CANFD_IPP_IND_CANRX: usize = 230;
+}
diff --git a/chips/imxrt1060/src/lib.rs b/chips/imxrt1060/src/lib.rs
new file mode 100644
index 0000000..0ac779b
--- /dev/null
+++ b/chips/imxrt1060/src/lib.rs
@@ -0,0 +1,54 @@
+#![no_std]
+
+pub use ral_registers::{Instance, modify_reg, read_reg, write_reg};
+
+mod rt;
+pub use rt::*;
+
+pub mod iomuxc;
+
+/// Clock control module.
+pub mod ccm {
+    pub use imxrt_drivers_ccm_10xx::ahb::pll1::*;
+
+    pub use imxrt_drivers_ccm_10xx::ccm::{
+        LowPowerMode, ahb_clk, clock_gate, flexspi1_clk_axi_semc as flexspi1_clk, ipg_clk,
+        low_power_mode, lpi2c_clk, lpspi_clk, perclk_clk, set_low_power_mode, uart_clk,
+    };
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::{pll2, pll3};
+
+    pub use imxrt_drivers_ccm_10xx::ccm::{
+        arm_divider, periph_clk2, pre_periph_clk_pll1 as pre_periph_clk,
+    };
+
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::pll7;
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::{pll1, pll6};
+}
+
+pub use imxrt_drivers_flexspi as flexspi;
+pub use imxrt_drivers_lpspi as lpspi;
+pub use imxrt_drivers_pit as pit;
+
+/// Peripheral instances.
+pub mod instances {
+    ral_registers::instances! {
+        // Safety: The reference manual confirms there are register
+        // blocks at this address matching this shape.
+        unsafe {
+            /// Access CCM registers.
+            pub ccm<imxrt_drivers_ccm_10xx::ral::ccm::RegisterBlock> = 0x400F_C000;
+            /// Access CCM\_ANALOG registers.
+            pub ccm_analog<imxrt_drivers_ccm_10xx::ral::ccm_analog::RegisterBlock> = 0x400D_8000;
+
+            pub flexspi1<crate::flexspi::RegisterBlock> = 0x402A_8000;
+            pub flexspi2<crate::flexspi::RegisterBlock> = 0x402A_4000;
+
+            pub pit<crate::pit::RegisterBlock> = 0x4008_4000;
+
+            pub lpspi1<crate::lpspi::RegisterBlock> = 0x4039_4000;
+            pub lpspi2<crate::lpspi::RegisterBlock> = 0x4039_8000;
+            pub lpspi3<crate::lpspi::RegisterBlock> = 0x4039_C000;
+            pub lpspi4<crate::lpspi::RegisterBlock> = 0x403A_0000;
+        }
+    }
+}
diff --git a/chips/imxrt1060/src/rt.rs b/chips/imxrt1060/src/rt.rs
new file mode 100644
index 0000000..a54aa2f
--- /dev/null
+++ b/chips/imxrt1060/src/rt.rs
@@ -0,0 +1,729 @@
+#![allow(non_camel_case_types)]
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - DMA0_DMA16"]
+    DMA0_DMA16 = 0,
+    #[doc = "1 - DMA1_DMA17"]
+    DMA1_DMA17 = 1,
+    #[doc = "2 - DMA2_DMA18"]
+    DMA2_DMA18 = 2,
+    #[doc = "3 - DMA3_DMA19"]
+    DMA3_DMA19 = 3,
+    #[doc = "4 - DMA4_DMA20"]
+    DMA4_DMA20 = 4,
+    #[doc = "5 - DMA5_DMA21"]
+    DMA5_DMA21 = 5,
+    #[doc = "6 - DMA6_DMA22"]
+    DMA6_DMA22 = 6,
+    #[doc = "7 - DMA7_DMA23"]
+    DMA7_DMA23 = 7,
+    #[doc = "8 - DMA8_DMA24"]
+    DMA8_DMA24 = 8,
+    #[doc = "9 - DMA9_DMA25"]
+    DMA9_DMA25 = 9,
+    #[doc = "10 - DMA10_DMA26"]
+    DMA10_DMA26 = 10,
+    #[doc = "11 - DMA11_DMA27"]
+    DMA11_DMA27 = 11,
+    #[doc = "12 - DMA12_DMA28"]
+    DMA12_DMA28 = 12,
+    #[doc = "13 - DMA13_DMA29"]
+    DMA13_DMA29 = 13,
+    #[doc = "14 - DMA14_DMA30"]
+    DMA14_DMA30 = 14,
+    #[doc = "15 - DMA15_DMA31"]
+    DMA15_DMA31 = 15,
+    #[doc = "16 - DMA_ERROR"]
+    DMA_ERROR = 16,
+    #[doc = "20 - LPUART1"]
+    LPUART1 = 20,
+    #[doc = "21 - LPUART2"]
+    LPUART2 = 21,
+    #[doc = "22 - LPUART3"]
+    LPUART3 = 22,
+    #[doc = "23 - LPUART4"]
+    LPUART4 = 23,
+    #[doc = "24 - LPUART5"]
+    LPUART5 = 24,
+    #[doc = "25 - LPUART6"]
+    LPUART6 = 25,
+    #[doc = "26 - LPUART7"]
+    LPUART7 = 26,
+    #[doc = "27 - LPUART8"]
+    LPUART8 = 27,
+    #[doc = "28 - LPI2C1"]
+    LPI2C1 = 28,
+    #[doc = "29 - LPI2C2"]
+    LPI2C2 = 29,
+    #[doc = "30 - LPI2C3"]
+    LPI2C3 = 30,
+    #[doc = "31 - LPI2C4"]
+    LPI2C4 = 31,
+    #[doc = "32 - LPSPI1"]
+    LPSPI1 = 32,
+    #[doc = "33 - LPSPI2"]
+    LPSPI2 = 33,
+    #[doc = "34 - LPSPI3"]
+    LPSPI3 = 34,
+    #[doc = "35 - LPSPI4"]
+    LPSPI4 = 35,
+    #[doc = "36 - CAN1"]
+    CAN1 = 36,
+    #[doc = "37 - CAN2"]
+    CAN2 = 37,
+    #[doc = "38 - FLEXRAM"]
+    FLEXRAM = 38,
+    #[doc = "39 - KPP"]
+    KPP = 39,
+    #[doc = "40 - TSC_DIG"]
+    TSC_DIG = 40,
+    #[doc = "41 - GPR (aka \"GPC\") interrupt request"]
+    GPR_IRQ = 41,
+    #[doc = "42 - LCDIF"]
+    LCDIF = 42,
+    #[doc = "43 - CSI"]
+    CSI = 43,
+    #[doc = "44 - PXP"]
+    PXP = 44,
+    #[doc = "45 - WDOG2"]
+    WDOG2 = 45,
+    #[doc = "46 - SNVS_HP_WRAPPER"]
+    SNVS_HP_WRAPPER = 46,
+    #[doc = "47 - SNVS_HP_WRAPPER_TZ"]
+    SNVS_HP_WRAPPER_TZ = 47,
+    #[doc = "48 - SNVS_LP_WRAPPER"]
+    SNVS_LP_WRAPPER = 48,
+    #[doc = "49 - CSU"]
+    CSU = 49,
+    #[doc = "50 - DCP"]
+    DCP = 50,
+    #[doc = "51 - DCP_VMI"]
+    DCP_VMI = 51,
+    #[doc = "53 - TRNG"]
+    TRNG = 53,
+    #[doc = "55 - BEE"]
+    BEE = 55,
+    #[doc = "56 - SAI1"]
+    SAI1 = 56,
+    #[doc = "57 - SAI2"]
+    SAI2 = 57,
+    #[doc = "58 - SAI3_RX"]
+    SAI3_RX = 58,
+    #[doc = "59 - SAI3_TX"]
+    SAI3_TX = 59,
+    #[doc = "60 - SPDIF"]
+    SPDIF = 60,
+    #[doc = "61 - PMU_EVENT"]
+    PMU_EVENT = 61,
+    #[doc = "63 - TEMP_LOW_HIGH"]
+    TEMP_LOW_HIGH = 63,
+    #[doc = "64 - TEMP_PANIC"]
+    TEMP_PANIC = 64,
+    #[doc = "65 - USB_PHY1"]
+    USB_PHY1 = 65,
+    #[doc = "66 - USB_PHY2"]
+    USB_PHY2 = 66,
+    #[doc = "67 - ADC1"]
+    ADC1 = 67,
+    #[doc = "68 - ADC2"]
+    ADC2 = 68,
+    #[doc = "69 - DCDC"]
+    DCDC = 69,
+    #[doc = "72 - GPIO1_INT0"]
+    GPIO1_INT0 = 72,
+    #[doc = "73 - GPIO1_INT1"]
+    GPIO1_INT1 = 73,
+    #[doc = "74 - GPIO1_INT2"]
+    GPIO1_INT2 = 74,
+    #[doc = "75 - GPIO1_INT3"]
+    GPIO1_INT3 = 75,
+    #[doc = "76 - GPIO1_INT4"]
+    GPIO1_INT4 = 76,
+    #[doc = "77 - GPIO1_INT5"]
+    GPIO1_INT5 = 77,
+    #[doc = "78 - GPIO1_INT6"]
+    GPIO1_INT6 = 78,
+    #[doc = "79 - GPIO1_INT7"]
+    GPIO1_INT7 = 79,
+    #[doc = "80 - GPIO1_COMBINED_0_15"]
+    GPIO1_COMBINED_0_15 = 80,
+    #[doc = "81 - GPIO1_COMBINED_16_31"]
+    GPIO1_COMBINED_16_31 = 81,
+    #[doc = "82 - GPIO2_COMBINED_0_15"]
+    GPIO2_COMBINED_0_15 = 82,
+    #[doc = "83 - GPIO2_COMBINED_16_31"]
+    GPIO2_COMBINED_16_31 = 83,
+    #[doc = "84 - GPIO3_COMBINED_0_15"]
+    GPIO3_COMBINED_0_15 = 84,
+    #[doc = "85 - GPIO3_COMBINED_16_31"]
+    GPIO3_COMBINED_16_31 = 85,
+    #[doc = "86 - GPIO4_COMBINED_0_15"]
+    GPIO4_COMBINED_0_15 = 86,
+    #[doc = "87 - GPIO4_COMBINED_16_31"]
+    GPIO4_COMBINED_16_31 = 87,
+    #[doc = "88 - GPIO5_COMBINED_0_15"]
+    GPIO5_COMBINED_0_15 = 88,
+    #[doc = "89 - GPIO5_COMBINED_16_31"]
+    GPIO5_COMBINED_16_31 = 89,
+    #[doc = "90 - FLEXIO1"]
+    FLEXIO1 = 90,
+    #[doc = "91 - FLEXIO2"]
+    FLEXIO2 = 91,
+    #[doc = "92 - WDOG1"]
+    WDOG1 = 92,
+    #[doc = "93 - RTWDOG"]
+    RTWDOG = 93,
+    #[doc = "94 - EWM"]
+    EWM = 94,
+    #[doc = "95 - CCM_1"]
+    CCM_1 = 95,
+    #[doc = "96 - CCM_2"]
+    CCM_2 = 96,
+    #[doc = "97 - GPC"]
+    GPC = 97,
+    #[doc = "98 - SRC"]
+    SRC = 98,
+    #[doc = "100 - GPT1"]
+    GPT1 = 100,
+    #[doc = "101 - GPT2"]
+    GPT2 = 101,
+    #[doc = "102 - PWM1_0"]
+    PWM1_0 = 102,
+    #[doc = "103 - PWM1_1"]
+    PWM1_1 = 103,
+    #[doc = "104 - PWM1_2"]
+    PWM1_2 = 104,
+    #[doc = "105 - PWM1_3"]
+    PWM1_3 = 105,
+    #[doc = "106 - PWM1_FAULT"]
+    PWM1_FAULT = 106,
+    #[doc = "107 - FLEXSPI2"]
+    FLEXSPI2 = 107,
+    #[doc = "108 - FLEXSPI"]
+    FLEXSPI = 108,
+    #[doc = "109 - SEMC"]
+    SEMC = 109,
+    #[doc = "110 - USDHC1"]
+    USDHC1 = 110,
+    #[doc = "111 - USDHC2"]
+    USDHC2 = 111,
+    #[doc = "112 - USB_OTG2"]
+    USB_OTG2 = 112,
+    #[doc = "113 - USB_OTG1"]
+    USB_OTG1 = 113,
+    #[doc = "114 - ENET"]
+    ENET = 114,
+    #[doc = "115 - ENET_1588_TIMER"]
+    ENET_1588_TIMER = 115,
+    #[doc = "116 - XBAR1_IRQ_0_1"]
+    XBAR1_IRQ_0_1 = 116,
+    #[doc = "117 - XBAR1_IRQ_2_3"]
+    XBAR1_IRQ_2_3 = 117,
+    #[doc = "118 - ADC_ETC_IRQ0"]
+    ADC_ETC_IRQ0 = 118,
+    #[doc = "119 - ADC_ETC_IRQ1"]
+    ADC_ETC_IRQ1 = 119,
+    #[doc = "120 - ADC_ETC_IRQ2"]
+    ADC_ETC_IRQ2 = 120,
+    #[doc = "121 - ADC_ETC_ERROR_IRQ"]
+    ADC_ETC_ERROR_IRQ = 121,
+    #[doc = "122 - PIT"]
+    PIT = 122,
+    #[doc = "123 - ACMP1"]
+    ACMP1 = 123,
+    #[doc = "124 - ACMP2"]
+    ACMP2 = 124,
+    #[doc = "125 - ACMP3"]
+    ACMP3 = 125,
+    #[doc = "126 - ACMP4"]
+    ACMP4 = 126,
+    #[doc = "129 - ENC1"]
+    ENC1 = 129,
+    #[doc = "130 - ENC2"]
+    ENC2 = 130,
+    #[doc = "131 - ENC3"]
+    ENC3 = 131,
+    #[doc = "132 - ENC4"]
+    ENC4 = 132,
+    #[doc = "133 - TMR1"]
+    TMR1 = 133,
+    #[doc = "134 - TMR2"]
+    TMR2 = 134,
+    #[doc = "135 - TMR3"]
+    TMR3 = 135,
+    #[doc = "136 - TMR4"]
+    TMR4 = 136,
+    #[doc = "137 - PWM2_0"]
+    PWM2_0 = 137,
+    #[doc = "138 - PWM2_1"]
+    PWM2_1 = 138,
+    #[doc = "139 - PWM2_2"]
+    PWM2_2 = 139,
+    #[doc = "140 - PWM2_3"]
+    PWM2_3 = 140,
+    #[doc = "141 - PWM2_FAULT"]
+    PWM2_FAULT = 141,
+    #[doc = "142 - PWM3_0"]
+    PWM3_0 = 142,
+    #[doc = "143 - PWM3_1"]
+    PWM3_1 = 143,
+    #[doc = "144 - PWM3_2"]
+    PWM3_2 = 144,
+    #[doc = "145 - PWM3_3"]
+    PWM3_3 = 145,
+    #[doc = "146 - PWM3_FAULT"]
+    PWM3_FAULT = 146,
+    #[doc = "147 - PWM4_0"]
+    PWM4_0 = 147,
+    #[doc = "148 - PWM4_1"]
+    PWM4_1 = 148,
+    #[doc = "149 - PWM4_2"]
+    PWM4_2 = 149,
+    #[doc = "150 - PWM4_3"]
+    PWM4_3 = 150,
+    #[doc = "151 - PWM4_FAULT"]
+    PWM4_FAULT = 151,
+    #[doc = "152 - ENET2"]
+    ENET2 = 152,
+    #[doc = "153 - ENET2_1588_TIMER"]
+    ENET2_1588_TIMER = 153,
+    #[doc = "154 - CAN3"]
+    CAN3 = 154,
+    #[doc = "156 - FLEXIO3"]
+    FLEXIO3 = 156,
+    #[doc = "157 - GPIO6_7_8_9"]
+    GPIO6_7_8_9 = 157,
+}
+pub type interrupt = Interrupt;
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+
+mod _vectors {
+    unsafe extern "C" {
+        fn DMA0_DMA16();
+        fn DMA1_DMA17();
+        fn DMA2_DMA18();
+        fn DMA3_DMA19();
+        fn DMA4_DMA20();
+        fn DMA5_DMA21();
+        fn DMA6_DMA22();
+        fn DMA7_DMA23();
+        fn DMA8_DMA24();
+        fn DMA9_DMA25();
+        fn DMA10_DMA26();
+        fn DMA11_DMA27();
+        fn DMA12_DMA28();
+        fn DMA13_DMA29();
+        fn DMA14_DMA30();
+        fn DMA15_DMA31();
+        fn DMA_ERROR();
+        fn LPUART1();
+        fn LPUART2();
+        fn LPUART3();
+        fn LPUART4();
+        fn LPUART5();
+        fn LPUART6();
+        fn LPUART7();
+        fn LPUART8();
+        fn LPI2C1();
+        fn LPI2C2();
+        fn LPI2C3();
+        fn LPI2C4();
+        fn LPSPI1();
+        fn LPSPI2();
+        fn LPSPI3();
+        fn LPSPI4();
+        fn CAN1();
+        fn CAN2();
+        fn FLEXRAM();
+        fn KPP();
+        fn TSC_DIG();
+        fn GPR_IRQ();
+        fn LCDIF();
+        fn CSI();
+        fn PXP();
+        fn WDOG2();
+        fn SNVS_HP_WRAPPER();
+        fn SNVS_HP_WRAPPER_TZ();
+        fn SNVS_LP_WRAPPER();
+        fn CSU();
+        fn DCP();
+        fn DCP_VMI();
+        fn TRNG();
+        fn BEE();
+        fn SAI1();
+        fn SAI2();
+        fn SAI3_RX();
+        fn SAI3_TX();
+        fn SPDIF();
+        fn PMU_EVENT();
+        fn TEMP_LOW_HIGH();
+        fn TEMP_PANIC();
+        fn USB_PHY1();
+        fn USB_PHY2();
+        fn ADC1();
+        fn ADC2();
+        fn DCDC();
+        fn GPIO1_INT0();
+        fn GPIO1_INT1();
+        fn GPIO1_INT2();
+        fn GPIO1_INT3();
+        fn GPIO1_INT4();
+        fn GPIO1_INT5();
+        fn GPIO1_INT6();
+        fn GPIO1_INT7();
+        fn GPIO1_COMBINED_0_15();
+        fn GPIO1_COMBINED_16_31();
+        fn GPIO2_COMBINED_0_15();
+        fn GPIO2_COMBINED_16_31();
+        fn GPIO3_COMBINED_0_15();
+        fn GPIO3_COMBINED_16_31();
+        fn GPIO4_COMBINED_0_15();
+        fn GPIO4_COMBINED_16_31();
+        fn GPIO5_COMBINED_0_15();
+        fn GPIO5_COMBINED_16_31();
+        fn FLEXIO1();
+        fn FLEXIO2();
+        fn WDOG1();
+        fn RTWDOG();
+        fn EWM();
+        fn CCM_1();
+        fn CCM_2();
+        fn GPC();
+        fn SRC();
+        fn GPT1();
+        fn GPT2();
+        fn PWM1_0();
+        fn PWM1_1();
+        fn PWM1_2();
+        fn PWM1_3();
+        fn PWM1_FAULT();
+        fn FLEXSPI2();
+        fn FLEXSPI();
+        fn SEMC();
+        fn USDHC1();
+        fn USDHC2();
+        fn USB_OTG2();
+        fn USB_OTG1();
+        fn ENET();
+        fn ENET_1588_TIMER();
+        fn XBAR1_IRQ_0_1();
+        fn XBAR1_IRQ_2_3();
+        fn ADC_ETC_IRQ0();
+        fn ADC_ETC_IRQ1();
+        fn ADC_ETC_IRQ2();
+        fn ADC_ETC_ERROR_IRQ();
+        fn PIT();
+        fn ACMP1();
+        fn ACMP2();
+        fn ACMP3();
+        fn ACMP4();
+        fn ENC1();
+        fn ENC2();
+        fn ENC3();
+        fn ENC4();
+        fn TMR1();
+        fn TMR2();
+        fn TMR3();
+        fn TMR4();
+        fn PWM2_0();
+        fn PWM2_1();
+        fn PWM2_2();
+        fn PWM2_3();
+        fn PWM2_FAULT();
+        fn PWM3_0();
+        fn PWM3_1();
+        fn PWM3_2();
+        fn PWM3_3();
+        fn PWM3_FAULT();
+        fn PWM4_0();
+        fn PWM4_1();
+        fn PWM4_2();
+        fn PWM4_3();
+        fn PWM4_FAULT();
+        fn ENET2();
+        fn ENET2_1588_TIMER();
+        fn CAN3();
+        fn FLEXIO3();
+        fn GPIO6_7_8_9();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".vector_table.interrupts"))]
+    #[unsafe(no_mangle)]
+    pub static __INTERRUPTS: [Vector; 158] = [
+        Vector {
+            _handler: DMA0_DMA16,
+        },
+        Vector {
+            _handler: DMA1_DMA17,
+        },
+        Vector {
+            _handler: DMA2_DMA18,
+        },
+        Vector {
+            _handler: DMA3_DMA19,
+        },
+        Vector {
+            _handler: DMA4_DMA20,
+        },
+        Vector {
+            _handler: DMA5_DMA21,
+        },
+        Vector {
+            _handler: DMA6_DMA22,
+        },
+        Vector {
+            _handler: DMA7_DMA23,
+        },
+        Vector {
+            _handler: DMA8_DMA24,
+        },
+        Vector {
+            _handler: DMA9_DMA25,
+        },
+        Vector {
+            _handler: DMA10_DMA26,
+        },
+        Vector {
+            _handler: DMA11_DMA27,
+        },
+        Vector {
+            _handler: DMA12_DMA28,
+        },
+        Vector {
+            _handler: DMA13_DMA29,
+        },
+        Vector {
+            _handler: DMA14_DMA30,
+        },
+        Vector {
+            _handler: DMA15_DMA31,
+        },
+        Vector {
+            _handler: DMA_ERROR,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: LPUART2 },
+        Vector { _handler: LPUART3 },
+        Vector { _handler: LPUART4 },
+        Vector { _handler: LPUART5 },
+        Vector { _handler: LPUART6 },
+        Vector { _handler: LPUART7 },
+        Vector { _handler: LPUART8 },
+        Vector { _handler: LPI2C1 },
+        Vector { _handler: LPI2C2 },
+        Vector { _handler: LPI2C3 },
+        Vector { _handler: LPI2C4 },
+        Vector { _handler: LPSPI1 },
+        Vector { _handler: LPSPI2 },
+        Vector { _handler: LPSPI3 },
+        Vector { _handler: LPSPI4 },
+        Vector { _handler: CAN1 },
+        Vector { _handler: CAN2 },
+        Vector { _handler: FLEXRAM },
+        Vector { _handler: KPP },
+        Vector { _handler: TSC_DIG },
+        Vector { _handler: GPR_IRQ },
+        Vector { _handler: LCDIF },
+        Vector { _handler: CSI },
+        Vector { _handler: PXP },
+        Vector { _handler: WDOG2 },
+        Vector {
+            _handler: SNVS_HP_WRAPPER,
+        },
+        Vector {
+            _handler: SNVS_HP_WRAPPER_TZ,
+        },
+        Vector {
+            _handler: SNVS_LP_WRAPPER,
+        },
+        Vector { _handler: CSU },
+        Vector { _handler: DCP },
+        Vector { _handler: DCP_VMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: TRNG },
+        Vector { _reserved: 0 },
+        Vector { _handler: BEE },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SAI3_RX },
+        Vector { _handler: SAI3_TX },
+        Vector { _handler: SPDIF },
+        Vector {
+            _handler: PMU_EVENT,
+        },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: TEMP_LOW_HIGH,
+        },
+        Vector {
+            _handler: TEMP_PANIC,
+        },
+        Vector { _handler: USB_PHY1 },
+        Vector { _handler: USB_PHY2 },
+        Vector { _handler: ADC1 },
+        Vector { _handler: ADC2 },
+        Vector { _handler: DCDC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: GPIO1_INT0,
+        },
+        Vector {
+            _handler: GPIO1_INT1,
+        },
+        Vector {
+            _handler: GPIO1_INT2,
+        },
+        Vector {
+            _handler: GPIO1_INT3,
+        },
+        Vector {
+            _handler: GPIO1_INT4,
+        },
+        Vector {
+            _handler: GPIO1_INT5,
+        },
+        Vector {
+            _handler: GPIO1_INT6,
+        },
+        Vector {
+            _handler: GPIO1_INT7,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_16_31,
+        },
+        Vector { _handler: FLEXIO1 },
+        Vector { _handler: FLEXIO2 },
+        Vector { _handler: WDOG1 },
+        Vector { _handler: RTWDOG },
+        Vector { _handler: EWM },
+        Vector { _handler: CCM_1 },
+        Vector { _handler: CCM_2 },
+        Vector { _handler: GPC },
+        Vector { _handler: SRC },
+        Vector { _reserved: 0 },
+        Vector { _handler: GPT1 },
+        Vector { _handler: GPT2 },
+        Vector { _handler: PWM1_0 },
+        Vector { _handler: PWM1_1 },
+        Vector { _handler: PWM1_2 },
+        Vector { _handler: PWM1_3 },
+        Vector {
+            _handler: PWM1_FAULT,
+        },
+        Vector { _handler: FLEXSPI2 },
+        Vector { _handler: FLEXSPI },
+        Vector { _handler: SEMC },
+        Vector { _handler: USDHC1 },
+        Vector { _handler: USDHC2 },
+        Vector { _handler: USB_OTG2 },
+        Vector { _handler: USB_OTG1 },
+        Vector { _handler: ENET },
+        Vector {
+            _handler: ENET_1588_TIMER,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_0_1,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_2_3,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ0,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ1,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ2,
+        },
+        Vector {
+            _handler: ADC_ETC_ERROR_IRQ,
+        },
+        Vector { _handler: PIT },
+        Vector { _handler: ACMP1 },
+        Vector { _handler: ACMP2 },
+        Vector { _handler: ACMP3 },
+        Vector { _handler: ACMP4 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: ENC1 },
+        Vector { _handler: ENC2 },
+        Vector { _handler: ENC3 },
+        Vector { _handler: ENC4 },
+        Vector { _handler: TMR1 },
+        Vector { _handler: TMR2 },
+        Vector { _handler: TMR3 },
+        Vector { _handler: TMR4 },
+        Vector { _handler: PWM2_0 },
+        Vector { _handler: PWM2_1 },
+        Vector { _handler: PWM2_2 },
+        Vector { _handler: PWM2_3 },
+        Vector {
+            _handler: PWM2_FAULT,
+        },
+        Vector { _handler: PWM3_0 },
+        Vector { _handler: PWM3_1 },
+        Vector { _handler: PWM3_2 },
+        Vector { _handler: PWM3_3 },
+        Vector {
+            _handler: PWM3_FAULT,
+        },
+        Vector { _handler: PWM4_0 },
+        Vector { _handler: PWM4_1 },
+        Vector { _handler: PWM4_2 },
+        Vector { _handler: PWM4_3 },
+        Vector {
+            _handler: PWM4_FAULT,
+        },
+        Vector { _handler: ENET2 },
+        Vector {
+            _handler: ENET2_1588_TIMER,
+        },
+        Vector { _handler: CAN3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FLEXIO3 },
+        Vector {
+            _handler: GPIO6_7_8_9,
+        },
+    ];
+}