First commit

33 files changed, 6929 insertions, 0 deletions

diff --git a/chips/imxrt1010/Cargo.toml b/chips/imxrt1010/Cargo.toml
new file mode 100644
index 0000000..2a00927
--- /dev/null
+++ b/chips/imxrt1010/Cargo.toml
@@ -0,0 +1,17 @@
+[package]
+name = "imxrt1010"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+cortex-m = { workspace = true }
+ral-registers = { workspace = true }
+
+imxrt-drivers-ccm-10xx = { workspace = true }
+imxrt-drivers-dcdc = { workspace = true }
+imxrt-drivers-gpio = { workspace = true }
+imxrt-drivers-flexspi = { workspace = true }
+imxrt-drivers-iomuxc-10xx = { workspace = true }
+imxrt-drivers-lpspi = { workspace = true }
+imxrt-drivers-pit = { workspace = true }
+imxrt-drivers-rtwdog = { workspace = true }
diff --git a/chips/imxrt1010/build.rs b/chips/imxrt1010/build.rs
new file mode 100644
index 0000000..3af590f
--- /dev/null
+++ b/chips/imxrt1010/build.rs
@@ -0,0 +1,8 @@
+use std::{env, fs, path};
+
+fn main() {
+    let out_dir = path::PathBuf::from(env::var("OUT_DIR").unwrap());
+    fs::copy("device.x", out_dir.join("device.x")).unwrap();
+    fs::copy("device.x", out_dir.join("imxrt1010.x")).unwrap();
+    println!("cargo::rustc-link-search={}", out_dir.display());
+}
diff --git a/chips/imxrt1010/device.x b/chips/imxrt1010/device.x
new file mode 100644
index 0000000..1d52693
--- /dev/null
+++ b/chips/imxrt1010/device.x
@@ -0,0 +1,74 @@
+PROVIDE(DMA0 = DefaultHandler);
+PROVIDE(DMA1 = DefaultHandler);
+PROVIDE(DMA2 = DefaultHandler);
+PROVIDE(DMA3 = DefaultHandler);
+PROVIDE(DMA4 = DefaultHandler);
+PROVIDE(DMA5 = DefaultHandler);
+PROVIDE(DMA6 = DefaultHandler);
+PROVIDE(DMA7 = DefaultHandler);
+PROVIDE(DMA8 = DefaultHandler);
+PROVIDE(DMA9 = DefaultHandler);
+PROVIDE(DMA10 = DefaultHandler);
+PROVIDE(DMA11 = DefaultHandler);
+PROVIDE(DMA12 = DefaultHandler);
+PROVIDE(DMA13 = DefaultHandler);
+PROVIDE(DMA14 = DefaultHandler);
+PROVIDE(DMA15 = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(LPUART1 = DefaultHandler);
+PROVIDE(LPUART2 = DefaultHandler);
+PROVIDE(LPUART3 = DefaultHandler);
+PROVIDE(LPUART4 = DefaultHandler);
+PROVIDE(PIT = DefaultHandler);
+PROVIDE(USB_OTG1 = DefaultHandler);
+PROVIDE(FLEXSPI = DefaultHandler);
+PROVIDE(FLEXRAM = DefaultHandler);
+PROVIDE(LPI2C1 = DefaultHandler);
+PROVIDE(LPI2C2 = DefaultHandler);
+PROVIDE(GPT1 = DefaultHandler);
+PROVIDE(GPT2 = DefaultHandler);
+PROVIDE(LPSPI1 = DefaultHandler);
+PROVIDE(LPSPI2 = DefaultHandler);
+PROVIDE(PWM1_0 = DefaultHandler);
+PROVIDE(PWM1_1 = DefaultHandler);
+PROVIDE(PWM1_2 = DefaultHandler);
+PROVIDE(PWM1_3 = DefaultHandler);
+PROVIDE(PWM1_FAULT = DefaultHandler);
+PROVIDE(KPP = DefaultHandler);
+PROVIDE(SRC = DefaultHandler);
+PROVIDE(GPR_IRQ = DefaultHandler);
+PROVIDE(CCM_1 = DefaultHandler);
+PROVIDE(CCM_2 = DefaultHandler);
+PROVIDE(EWM = DefaultHandler);
+PROVIDE(WDOG2 = DefaultHandler);
+PROVIDE(SNVS_HP_WRAPPER = DefaultHandler);
+PROVIDE(SNVS_HP_WRAPPER_TZ = DefaultHandler);
+PROVIDE(SNVS_LP_WRAPPER = DefaultHandler);
+PROVIDE(CSU = DefaultHandler);
+PROVIDE(DCP = DefaultHandler);
+PROVIDE(DCP_VMI = DefaultHandler);
+PROVIDE(TRNG = DefaultHandler);
+PROVIDE(SAI1 = DefaultHandler);
+PROVIDE(RTWDOG = DefaultHandler);
+PROVIDE(SAI3_RX = DefaultHandler);
+PROVIDE(SAI3_TX = DefaultHandler);
+PROVIDE(SPDIF = DefaultHandler);
+PROVIDE(PMU = DefaultHandler);
+PROVIDE(XBAR1_IRQ_0_1_2_3 = DefaultHandler);
+PROVIDE(TEMP_LOW_HIGH = DefaultHandler);
+PROVIDE(TEMP_PANIC = DefaultHandler);
+PROVIDE(USB_PHY = DefaultHandler);
+PROVIDE(GPC = DefaultHandler);
+PROVIDE(ADC1 = DefaultHandler);
+PROVIDE(FLEXIO1 = DefaultHandler);
+PROVIDE(DCDC = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_0_15 = DefaultHandler);
+PROVIDE(WDOG1 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ0 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ1 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ2 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ3 = DefaultHandler);
+PROVIDE(ADC_ETC_ERROR_IRQ = DefaultHandler);
diff --git a/chips/imxrt1010/src/iomuxc.rs b/chips/imxrt1010/src/iomuxc.rs
new file mode 100644
index 0000000..7745808
--- /dev/null
+++ b/chips/imxrt1010/src/iomuxc.rs
@@ -0,0 +1,100 @@
+pub type RegisterBlock = imxrt_drivers_iomuxc_10xx::iomuxc::RegisterBlock<16, 44, 45>;
+
+pub use imxrt_drivers_iomuxc_10xx::iomuxc::{SELECT_INPUT, SW_MUX_CTL_PAD, SW_PAD_CTL_PAD};
+
+/// Indices for `sw_[pad|mux]_ctl_pad` registers.
+pub mod pad {
+    pub const GPIO_AD_14: usize = 0;
+    pub const GPIO_AD_13: usize = 1;
+    pub const GPIO_AD_12: usize = 2;
+    pub const GPIO_AD_11: usize = 3;
+    pub const GPIO_AD_10: usize = 4;
+    pub const GPIO_AD_09: usize = 5;
+    pub const GPIO_AD_08: usize = 6;
+    pub const GPIO_AD_07: usize = 7;
+    pub const GPIO_AD_06: usize = 8;
+    pub const GPIO_AD_05: usize = 9;
+    pub const GPIO_AD_04: usize = 10;
+    pub const GPIO_AD_03: usize = 11;
+    pub const GPIO_AD_02: usize = 12;
+    pub const GPIO_AD_01: usize = 13;
+    pub const GPIO_AD_00: usize = 14;
+    pub const GPIO_SD_14: usize = 15;
+    pub const GPIO_SD_13: usize = 16;
+    pub const GPIO_SD_12: usize = 17;
+    pub const GPIO_SD_11: usize = 18;
+    pub const GPIO_SD_10: usize = 19;
+    pub const GPIO_SD_09: usize = 20;
+    pub const GPIO_SD_08: usize = 21;
+    pub const GPIO_SD_07: usize = 22;
+    pub const GPIO_SD_06: usize = 23;
+    pub const GPIO_SD_05: usize = 24;
+    pub const GPIO_SD_04: usize = 25;
+    pub const GPIO_SD_03: usize = 26;
+    pub const GPIO_SD_02: usize = 27;
+    pub const GPIO_SD_01: usize = 28;
+    pub const GPIO_SD_00: usize = 29;
+    pub const GPIO_13: usize = 30;
+    pub const GPIO_12: usize = 31;
+    pub const GPIO_11: usize = 32;
+    pub const GPIO_10: usize = 33;
+    pub const GPIO_09: usize = 34;
+    pub const GPIO_08: usize = 35;
+    pub const GPIO_07: usize = 36;
+    pub const GPIO_06: usize = 37;
+    pub const GPIO_05: usize = 38;
+    pub const GPIO_04: usize = 39;
+    pub const GPIO_03: usize = 40;
+    pub const GPIO_02: usize = 41;
+    pub const GPIO_01: usize = 42;
+    pub const GPIO_00: usize = 43;
+}
+
+/// Indices for `select_input` registers.
+pub mod select_input {
+    pub const USB_OTG_ID: usize = 0;
+    pub const FLEXPWM1_PWMA_0: usize = 1;
+    pub const FLEXPWM1_PWMA_1: usize = 2;
+    pub const FLEXPWM1_PWMA_2: usize = 3;
+    pub const FLEXPWM1_PWMA_3: usize = 4;
+    pub const FLEXPWM1_PWMB_0: usize = 5;
+    pub const FLEXPWM1_PWMB_1: usize = 6;
+    pub const FLEXPWM1_PWMB_2: usize = 7;
+    pub const FLEXPWM1_PWMB_3: usize = 8;
+    pub const FLEXSPI_DQS_FA: usize = 9;
+    pub const FLEXSPI_DQS_FB: usize = 10;
+    pub const KPP_COL_0: usize = 11;
+    pub const KPP_COL_1: usize = 12;
+    pub const KPP_COL_2: usize = 13;
+    pub const KPP_COL_3: usize = 14;
+    pub const KPP_ROW_0: usize = 15;
+    pub const KPP_ROW_1: usize = 16;
+    pub const KPP_ROW_2: usize = 17;
+    pub const KPP_ROW_3: usize = 18;
+    pub const LPI2C1_HREQ: usize = 19;
+    pub const LPI2C1_SCL: usize = 20;
+    pub const LPI2C1_SDA: usize = 21;
+    pub const LPI2C2_SCL: usize = 22;
+    pub const LPI2C2_SDA: usize = 23;
+    pub const LPSPI1_PCS: usize = 24;
+    pub const LPSPI1_SCK: usize = 25;
+    pub const LPSPI1_SDI: usize = 26;
+    pub const LPSPI1_SDO: usize = 27;
+    pub const LPSPI2_PCS: usize = 28;
+    pub const LPSPI2_SCK: usize = 29;
+    pub const LPSPI2_SDI: usize = 30;
+    pub const LPSPI2_SDO: usize = 31;
+    pub const LPUART1_RXD: usize = 32;
+    pub const LPUART1_TXD: usize = 33;
+    pub const LPUART2_RXD: usize = 34;
+    pub const LPUART2_TXD: usize = 35;
+    pub const LPUART3_RXD: usize = 36;
+    pub const LPUART3_TXD: usize = 37;
+    pub const LPUART4_RXD: usize = 38;
+    pub const LPUART4_TXD: usize = 39;
+    pub const NMI_GLUE_NMI: usize = 40;
+    pub const SPDIF_IN1: usize = 41;
+    pub const SPDIF_TX_CLK2: usize = 42;
+    pub const USB_OTG_OC: usize = 43;
+    pub const XEV_GLUE_RXEV: usize = 44;
+}
diff --git a/chips/imxrt1010/src/lib.rs b/chips/imxrt1010/src/lib.rs
new file mode 100644
index 0000000..1c45430
--- /dev/null
+++ b/chips/imxrt1010/src/lib.rs
@@ -0,0 +1,76 @@
+//! Drivers for iMXRT1010 MCUs.
+
+#![no_std]
+
+pub use ral_registers::{Instance, modify_reg, read_reg, write_reg};
+
+mod rt;
+pub use rt::*;
+
+pub mod iomuxc;
+
+/// Clock control module.
+pub mod ccm {
+    pub use imxrt_drivers_ccm_10xx::ahb::pll6_500mhz::*;
+
+    pub use imxrt_drivers_ccm_10xx::ccm::{
+        CCM, LowPowerMode, ahb_clk, clock_gate, flexspi1_clk_root_pll2 as flexspi1_clk, ipg_clk,
+        low_power_mode, lpi2c_clk, lpspi_clk, perclk_clk, set_low_power_mode, uart_clk,
+    };
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::{CCM_ANALOG, pll2, pll3};
+
+    /// Peripheral clock 2.
+    pub mod periph_clk2 {
+        pub use imxrt_drivers_ccm_10xx::ccm::periph_clk2::{Selection, selection, set_selection};
+    }
+
+    pub use imxrt_drivers_ccm_10xx::ccm::pre_periph_clk_pll6 as pre_periph_clk;
+
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::pll6_500mhz as pll6;
+
+    pub mod gates {
+        use super::clock_gate::Locator::{self, *};
+
+        pub const FLEXSPI: Locator = Ccgr6Cg05;
+    }
+
+    pub use imxrt_drivers_ccm_10xx::ral;
+}
+
+pub use imxrt_drivers_dcdc as dcdc;
+pub use imxrt_drivers_flexspi as flexspi;
+pub use imxrt_drivers_gpio as gpio;
+pub use imxrt_drivers_lpspi as lpspi;
+pub use imxrt_drivers_pit as pit;
+pub use imxrt_drivers_rtwdog as rtwdog;
+
+/// Peripheral instances.
+pub mod instances {
+    ral_registers::instances! {
+        // Safety: The reference manual confirms there are register
+        // blocks at this address matching this shape.
+        unsafe {
+            /// Access CCM registers.
+            pub ccm<imxrt_drivers_ccm_10xx::ral::ccm::RegisterBlock> = 0x400F_C000;
+            /// Access CCM\_ANALOG registers.
+            pub ccm_analog<imxrt_drivers_ccm_10xx::ral::ccm_analog::RegisterBlock> = 0x400D_8000;
+
+            pub dcdc<crate::dcdc::RegisterBlock> = 0x4008_0000;
+
+            pub gpio1<crate::gpio::RegisterBlock> = 0x401b_8000;
+            pub gpio5<crate::gpio::RegisterBlock> = 0x400c_0000;
+            pub gpio2<crate::gpio::RegisterBlock> = 0x4200_0000;
+
+            pub iomuxc<crate::iomuxc::RegisterBlock> = 0x401F_8000;
+
+            pub flexspi<crate::flexspi::RegisterBlock> = 0x400A_0000;
+
+            pub pit<crate::pit::RegisterBlock> = 0x4008_4000;
+
+            pub lpspi1<crate::lpspi::RegisterBlock> = 0x4019_4000;
+            pub lpspi2<crate::lpspi::RegisterBlock> = 0x4019_8000;
+
+            pub wdog3<crate::rtwdog::RegisterBlock> = 0x400B_C000;
+        }
+    }
+}
diff --git a/chips/imxrt1010/src/rt.rs b/chips/imxrt1010/src/rt.rs
new file mode 100644
index 0000000..2fdbec8
--- /dev/null
+++ b/chips/imxrt1010/src/rt.rs
@@ -0,0 +1,361 @@
+#![allow(non_camel_case_types)]
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - DMA0"]
+    DMA0 = 0,
+    #[doc = "1 - DMA1"]
+    DMA1 = 1,
+    #[doc = "2 - DMA2"]
+    DMA2 = 2,
+    #[doc = "3 - DMA3"]
+    DMA3 = 3,
+    #[doc = "4 - DMA4"]
+    DMA4 = 4,
+    #[doc = "5 - DMA5"]
+    DMA5 = 5,
+    #[doc = "6 - DMA6"]
+    DMA6 = 6,
+    #[doc = "7 - DMA7"]
+    DMA7 = 7,
+    #[doc = "8 - DMA8"]
+    DMA8 = 8,
+    #[doc = "9 - DMA9"]
+    DMA9 = 9,
+    #[doc = "10 - DMA10"]
+    DMA10 = 10,
+    #[doc = "11 - DMA11"]
+    DMA11 = 11,
+    #[doc = "12 - DMA12"]
+    DMA12 = 12,
+    #[doc = "13 - DMA13"]
+    DMA13 = 13,
+    #[doc = "14 - DMA14"]
+    DMA14 = 14,
+    #[doc = "15 - DMA15"]
+    DMA15 = 15,
+    #[doc = "16 - DMA_ERROR"]
+    DMA_ERROR = 16,
+    #[doc = "20 - LPUART1"]
+    LPUART1 = 20,
+    #[doc = "21 - LPUART2"]
+    LPUART2 = 21,
+    #[doc = "22 - LPUART3"]
+    LPUART3 = 22,
+    #[doc = "23 - LPUART4"]
+    LPUART4 = 23,
+    #[doc = "24 - PIT"]
+    PIT = 24,
+    #[doc = "25 - USB_OTG1"]
+    USB_OTG1 = 25,
+    #[doc = "26 - FLEXSPI"]
+    FLEXSPI = 26,
+    #[doc = "27 - FLEXRAM"]
+    FLEXRAM = 27,
+    #[doc = "28 - LPI2C1"]
+    LPI2C1 = 28,
+    #[doc = "29 - LPI2C2"]
+    LPI2C2 = 29,
+    #[doc = "30 - GPT1"]
+    GPT1 = 30,
+    #[doc = "31 - GPT2"]
+    GPT2 = 31,
+    #[doc = "32 - LPSPI1"]
+    LPSPI1 = 32,
+    #[doc = "33 - LPSPI2"]
+    LPSPI2 = 33,
+    #[doc = "34 - PWM1_0"]
+    PWM1_0 = 34,
+    #[doc = "35 - PWM1_1"]
+    PWM1_1 = 35,
+    #[doc = "36 - PWM1_2"]
+    PWM1_2 = 36,
+    #[doc = "37 - PWM1_3"]
+    PWM1_3 = 37,
+    #[doc = "38 - PWM1_FAULT"]
+    PWM1_FAULT = 38,
+    #[doc = "39 - KPP"]
+    KPP = 39,
+    #[doc = "40 - SRC"]
+    SRC = 40,
+    #[doc = "41 - GPR (aka \"GPC\") interrupt request"]
+    GPR_IRQ = 41,
+    #[doc = "42 - CCM_1"]
+    CCM_1 = 42,
+    #[doc = "43 - CCM_2"]
+    CCM_2 = 43,
+    #[doc = "44 - EWM"]
+    EWM = 44,
+    #[doc = "45 - WDOG2"]
+    WDOG2 = 45,
+    #[doc = "46 - SNVS_HP_WRAPPER"]
+    SNVS_HP_WRAPPER = 46,
+    #[doc = "47 - SNVS_HP_WRAPPER_TZ"]
+    SNVS_HP_WRAPPER_TZ = 47,
+    #[doc = "48 - SNVS_LP_WRAPPER"]
+    SNVS_LP_WRAPPER = 48,
+    #[doc = "49 - CSU"]
+    CSU = 49,
+    #[doc = "50 - DCP"]
+    DCP = 50,
+    #[doc = "51 - DCP_VMI"]
+    DCP_VMI = 51,
+    #[doc = "53 - TRNG"]
+    TRNG = 53,
+    #[doc = "56 - SAI1"]
+    SAI1 = 56,
+    #[doc = "57 - RTWDOG"]
+    RTWDOG = 57,
+    #[doc = "58 - SAI3_RX"]
+    SAI3_RX = 58,
+    #[doc = "59 - SAI3_TX"]
+    SAI3_TX = 59,
+    #[doc = "60 - SPDIF"]
+    SPDIF = 60,
+    #[doc = "61 - PMU"]
+    PMU = 61,
+    #[doc = "62 - XBAR1_IRQ_0_1_2_3"]
+    XBAR1_IRQ_0_1_2_3 = 62,
+    #[doc = "63 - TEMP_LOW_HIGH"]
+    TEMP_LOW_HIGH = 63,
+    #[doc = "64 - TEMP_PANIC"]
+    TEMP_PANIC = 64,
+    #[doc = "65 - USB_PHY"]
+    USB_PHY = 65,
+    #[doc = "66 - GPC"]
+    GPC = 66,
+    #[doc = "67 - ADC1"]
+    ADC1 = 67,
+    #[doc = "68 - FLEXIO1"]
+    FLEXIO1 = 68,
+    #[doc = "69 - DCDC"]
+    DCDC = 69,
+    #[doc = "70 - GPIO1_COMBINED_0_15"]
+    GPIO1_COMBINED_0_15 = 70,
+    #[doc = "71 - GPIO1_COMBINED_16_31"]
+    GPIO1_COMBINED_16_31 = 71,
+    #[doc = "72 - GPIO2_COMBINED_0_15"]
+    GPIO2_COMBINED_0_15 = 72,
+    #[doc = "73 - GPIO5_COMBINED_0_15"]
+    GPIO5_COMBINED_0_15 = 73,
+    #[doc = "74 - WDOG1"]
+    WDOG1 = 74,
+    #[doc = "75 - ADC_ETC_IRQ0"]
+    ADC_ETC_IRQ0 = 75,
+    #[doc = "76 - ADC_ETC_IRQ1"]
+    ADC_ETC_IRQ1 = 76,
+    #[doc = "77 - ADC_ETC_IRQ2"]
+    ADC_ETC_IRQ2 = 77,
+    #[doc = "78 - ADC_ETC_IRQ3"]
+    ADC_ETC_IRQ3 = 78,
+    #[doc = "79 - ADC_ETC_ERROR_IRQ"]
+    ADC_ETC_ERROR_IRQ = 79,
+}
+pub type interrupt = Interrupt;
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+
+mod _vectors {
+    unsafe extern "C" {
+        fn DMA0();
+        fn DMA1();
+        fn DMA2();
+        fn DMA3();
+        fn DMA4();
+        fn DMA5();
+        fn DMA6();
+        fn DMA7();
+        fn DMA8();
+        fn DMA9();
+        fn DMA10();
+        fn DMA11();
+        fn DMA12();
+        fn DMA13();
+        fn DMA14();
+        fn DMA15();
+        fn DMA_ERROR();
+        fn LPUART1();
+        fn LPUART2();
+        fn LPUART3();
+        fn LPUART4();
+        fn PIT();
+        fn USB_OTG1();
+        fn FLEXSPI();
+        fn FLEXRAM();
+        fn LPI2C1();
+        fn LPI2C2();
+        fn GPT1();
+        fn GPT2();
+        fn LPSPI1();
+        fn LPSPI2();
+        fn PWM1_0();
+        fn PWM1_1();
+        fn PWM1_2();
+        fn PWM1_3();
+        fn PWM1_FAULT();
+        fn KPP();
+        fn SRC();
+        fn GPR_IRQ();
+        fn CCM_1();
+        fn CCM_2();
+        fn EWM();
+        fn WDOG2();
+        fn SNVS_HP_WRAPPER();
+        fn SNVS_HP_WRAPPER_TZ();
+        fn SNVS_LP_WRAPPER();
+        fn CSU();
+        fn DCP();
+        fn DCP_VMI();
+        fn TRNG();
+        fn SAI1();
+        fn RTWDOG();
+        fn SAI3_RX();
+        fn SAI3_TX();
+        fn SPDIF();
+        fn PMU();
+        fn XBAR1_IRQ_0_1_2_3();
+        fn TEMP_LOW_HIGH();
+        fn TEMP_PANIC();
+        fn USB_PHY();
+        fn GPC();
+        fn ADC1();
+        fn FLEXIO1();
+        fn DCDC();
+        fn GPIO1_COMBINED_0_15();
+        fn GPIO1_COMBINED_16_31();
+        fn GPIO2_COMBINED_0_15();
+        fn GPIO5_COMBINED_0_15();
+        fn WDOG1();
+        fn ADC_ETC_IRQ0();
+        fn ADC_ETC_IRQ1();
+        fn ADC_ETC_IRQ2();
+        fn ADC_ETC_IRQ3();
+        fn ADC_ETC_ERROR_IRQ();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".vector_table.interrupts"))]
+    #[unsafe(no_mangle)]
+    pub static __INTERRUPTS: [Vector; 80] = [
+        Vector { _handler: DMA0 },
+        Vector { _handler: DMA1 },
+        Vector { _handler: DMA2 },
+        Vector { _handler: DMA3 },
+        Vector { _handler: DMA4 },
+        Vector { _handler: DMA5 },
+        Vector { _handler: DMA6 },
+        Vector { _handler: DMA7 },
+        Vector { _handler: DMA8 },
+        Vector { _handler: DMA9 },
+        Vector { _handler: DMA10 },
+        Vector { _handler: DMA11 },
+        Vector { _handler: DMA12 },
+        Vector { _handler: DMA13 },
+        Vector { _handler: DMA14 },
+        Vector { _handler: DMA15 },
+        Vector {
+            _handler: DMA_ERROR,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: LPUART2 },
+        Vector { _handler: LPUART3 },
+        Vector { _handler: LPUART4 },
+        Vector { _handler: PIT },
+        Vector { _handler: USB_OTG1 },
+        Vector { _handler: FLEXSPI },
+        Vector { _handler: FLEXRAM },
+        Vector { _handler: LPI2C1 },
+        Vector { _handler: LPI2C2 },
+        Vector { _handler: GPT1 },
+        Vector { _handler: GPT2 },
+        Vector { _handler: LPSPI1 },
+        Vector { _handler: LPSPI2 },
+        Vector { _handler: PWM1_0 },
+        Vector { _handler: PWM1_1 },
+        Vector { _handler: PWM1_2 },
+        Vector { _handler: PWM1_3 },
+        Vector {
+            _handler: PWM1_FAULT,
+        },
+        Vector { _handler: KPP },
+        Vector { _handler: SRC },
+        Vector { _handler: GPR_IRQ },
+        Vector { _handler: CCM_1 },
+        Vector { _handler: CCM_2 },
+        Vector { _handler: EWM },
+        Vector { _handler: WDOG2 },
+        Vector {
+            _handler: SNVS_HP_WRAPPER,
+        },
+        Vector {
+            _handler: SNVS_HP_WRAPPER_TZ,
+        },
+        Vector {
+            _handler: SNVS_LP_WRAPPER,
+        },
+        Vector { _handler: CSU },
+        Vector { _handler: DCP },
+        Vector { _handler: DCP_VMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: TRNG },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: RTWDOG },
+        Vector { _handler: SAI3_RX },
+        Vector { _handler: SAI3_TX },
+        Vector { _handler: SPDIF },
+        Vector { _handler: PMU },
+        Vector {
+            _handler: XBAR1_IRQ_0_1_2_3,
+        },
+        Vector {
+            _handler: TEMP_LOW_HIGH,
+        },
+        Vector {
+            _handler: TEMP_PANIC,
+        },
+        Vector { _handler: USB_PHY },
+        Vector { _handler: GPC },
+        Vector { _handler: ADC1 },
+        Vector { _handler: FLEXIO1 },
+        Vector { _handler: DCDC },
+        Vector {
+            _handler: GPIO1_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_0_15,
+        },
+        Vector { _handler: WDOG1 },
+        Vector {
+            _handler: ADC_ETC_IRQ0,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ1,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ2,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ3,
+        },
+        Vector {
+            _handler: ADC_ETC_ERROR_IRQ,
+        },
+    ];
+}
diff --git a/chips/imxrt1040/Cargo.toml b/chips/imxrt1040/Cargo.toml
new file mode 100644
index 0000000..937783d
--- /dev/null
+++ b/chips/imxrt1040/Cargo.toml
@@ -0,0 +1,19 @@
+[package]
+name = "imxrt1040"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+cortex-m = { workspace = true }
+ral-registers = { workspace = true }
+
+imxrt-drivers-ccm-10xx = { workspace = true }
+imxrt-drivers-dcdc = { workspace = true }
+imxrt-drivers-edma = { workspace = true }
+imxrt-drivers-enet = { workspace = true }
+imxrt-drivers-flexspi = { workspace = true }
+imxrt-drivers-gpio = { workspace = true }
+imxrt-drivers-iomuxc-10xx = { workspace = true }
+imxrt-drivers-lpspi= { workspace = true }
+imxrt-drivers-pit = { workspace = true }
+imxrt-drivers-rtwdog = { workspace = true }
diff --git a/chips/imxrt1040/build.rs b/chips/imxrt1040/build.rs
new file mode 100644
index 0000000..1fb8515
--- /dev/null
+++ b/chips/imxrt1040/build.rs
@@ -0,0 +1,8 @@
+use std::{env, fs, path};
+
+fn main() {
+    let out_dir = path::PathBuf::from(env::var("OUT_DIR").unwrap());
+    fs::copy("device.x", out_dir.join("device.x")).unwrap();
+    fs::copy("device.x", out_dir.join("imxrt1040.x")).unwrap();
+    println!("cargo::rustc-link-search={}", out_dir.display());
+}
diff --git a/chips/imxrt1040/device.x b/chips/imxrt1040/device.x
new file mode 100644
index 0000000..99ae240
--- /dev/null
+++ b/chips/imxrt1040/device.x
@@ -0,0 +1,138 @@
+PROVIDE(DMA0_DMA16 = DefaultHandler);
+PROVIDE(DMA1_DMA17 = DefaultHandler);
+PROVIDE(DMA2_DMA18 = DefaultHandler);
+PROVIDE(DMA3_DMA19 = DefaultHandler);
+PROVIDE(DMA4_DMA20 = DefaultHandler);
+PROVIDE(DMA5_DMA21 = DefaultHandler);
+PROVIDE(DMA6_DMA22 = DefaultHandler);
+PROVIDE(DMA7_DMA23 = DefaultHandler);
+PROVIDE(DMA8_DMA24 = DefaultHandler);
+PROVIDE(DMA9_DMA25 = DefaultHandler);
+PROVIDE(DMA10_DMA26 = DefaultHandler);
+PROVIDE(DMA11_DMA27 = DefaultHandler);
+PROVIDE(DMA12_DMA28 = DefaultHandler);
+PROVIDE(DMA13_DMA29 = DefaultHandler);
+PROVIDE(DMA14_DMA30 = DefaultHandler);
+PROVIDE(DMA15_DMA31 = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(LPUART1 = DefaultHandler);
+PROVIDE(LPUART2 = DefaultHandler);
+PROVIDE(LPUART3 = DefaultHandler);
+PROVIDE(LPUART4 = DefaultHandler);
+PROVIDE(LPUART5 = DefaultHandler);
+PROVIDE(LPUART6 = DefaultHandler);
+PROVIDE(LPUART7 = DefaultHandler);
+PROVIDE(LPUART8 = DefaultHandler);
+PROVIDE(LPI2C1 = DefaultHandler);
+PROVIDE(LPI2C2 = DefaultHandler);
+PROVIDE(LPI2C3 = DefaultHandler);
+PROVIDE(LPI2C4 = DefaultHandler);
+PROVIDE(LPSPI1 = DefaultHandler);
+PROVIDE(LPSPI2 = DefaultHandler);
+PROVIDE(LPSPI3 = DefaultHandler);
+PROVIDE(CAN1 = DefaultHandler);
+PROVIDE(CAN2 = DefaultHandler);
+PROVIDE(FLEXRAM = DefaultHandler);
+PROVIDE(GPR_IRQ = DefaultHandler);
+PROVIDE(LCDIF = DefaultHandler);
+PROVIDE(PXP = DefaultHandler);
+PROVIDE(WDOG2 = DefaultHandler);
+PROVIDE(SNVS_HP_WRAPPER = DefaultHandler);
+PROVIDE(SNVS_HP_WRAPPER_TZ = DefaultHandler);
+PROVIDE(SNVS_LP_WRAPPER = DefaultHandler);
+PROVIDE(CSU = DefaultHandler);
+PROVIDE(DCP = DefaultHandler);
+PROVIDE(DCP_VMI = DefaultHandler);
+PROVIDE(TRNG = DefaultHandler);
+PROVIDE(BEE = DefaultHandler);
+PROVIDE(SAI1 = DefaultHandler);
+PROVIDE(SAI2 = DefaultHandler);
+PROVIDE(SAI3_RX = DefaultHandler);
+PROVIDE(SAI3_TX = DefaultHandler);
+PROVIDE(SPDIF = DefaultHandler);
+PROVIDE(PMU_EVENT = DefaultHandler);
+PROVIDE(TEMP_LOW_HIGH = DefaultHandler);
+PROVIDE(TEMP_PANIC = DefaultHandler);
+PROVIDE(USB_PHY1 = DefaultHandler);
+PROVIDE(ADC1 = DefaultHandler);
+PROVIDE(ADC2 = DefaultHandler);
+PROVIDE(DCDC = DefaultHandler);
+PROVIDE(GPIO1_INT0 = DefaultHandler);
+PROVIDE(GPIO1_INT1 = DefaultHandler);
+PROVIDE(GPIO1_INT2 = DefaultHandler);
+PROVIDE(GPIO1_INT3 = DefaultHandler);
+PROVIDE(GPIO1_INT4 = DefaultHandler);
+PROVIDE(GPIO1_INT5 = DefaultHandler);
+PROVIDE(GPIO1_INT6 = DefaultHandler);
+PROVIDE(GPIO1_INT7 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO3_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO3_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO4_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO4_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_16_31 = DefaultHandler);
+PROVIDE(FLEXIO1 = DefaultHandler);
+PROVIDE(FLEXIO2 = DefaultHandler);
+PROVIDE(WDOG1 = DefaultHandler);
+PROVIDE(RTWDOG = DefaultHandler);
+PROVIDE(EWM = DefaultHandler);
+PROVIDE(CCM_1 = DefaultHandler);
+PROVIDE(CCM_2 = DefaultHandler);
+PROVIDE(GPC = DefaultHandler);
+PROVIDE(SRC = DefaultHandler);
+PROVIDE(GPT1 = DefaultHandler);
+PROVIDE(GPT2 = DefaultHandler);
+PROVIDE(PWM1_0 = DefaultHandler);
+PROVIDE(PWM1_1 = DefaultHandler);
+PROVIDE(PWM1_2 = DefaultHandler);
+PROVIDE(PWM1_3 = DefaultHandler);
+PROVIDE(PWM1_FAULT = DefaultHandler);
+PROVIDE(FLEXSPI2 = DefaultHandler);
+PROVIDE(FLEXSPI = DefaultHandler);
+PROVIDE(SEMC = DefaultHandler);
+PROVIDE(USDHC1 = DefaultHandler);
+PROVIDE(USDHC2 = DefaultHandler);
+PROVIDE(USB_OTG1 = DefaultHandler);
+PROVIDE(ENET = DefaultHandler);
+PROVIDE(ENET_1588_TIMER = DefaultHandler);
+PROVIDE(XBAR1_IRQ_0_1 = DefaultHandler);
+PROVIDE(XBAR1_IRQ_2_3 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ0 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ1 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ2 = DefaultHandler);
+PROVIDE(ADC_ETC_ERROR_IRQ = DefaultHandler);
+PROVIDE(PIT = DefaultHandler);
+PROVIDE(ACMP1 = DefaultHandler);
+PROVIDE(ACMP2 = DefaultHandler);
+PROVIDE(ACMP3 = DefaultHandler);
+PROVIDE(ACMP4 = DefaultHandler);
+PROVIDE(ENC1 = DefaultHandler);
+PROVIDE(ENC2 = DefaultHandler);
+PROVIDE(ENC3 = DefaultHandler);
+PROVIDE(ENC4 = DefaultHandler);
+PROVIDE(TMR1 = DefaultHandler);
+PROVIDE(TMR2 = DefaultHandler);
+PROVIDE(TMR3 = DefaultHandler);
+PROVIDE(TMR4 = DefaultHandler);
+PROVIDE(PWM2_0 = DefaultHandler);
+PROVIDE(PWM2_1 = DefaultHandler);
+PROVIDE(PWM2_2 = DefaultHandler);
+PROVIDE(PWM2_3 = DefaultHandler);
+PROVIDE(PWM2_FAULT = DefaultHandler);
+PROVIDE(PWM3_0 = DefaultHandler);
+PROVIDE(PWM3_1 = DefaultHandler);
+PROVIDE(PWM3_2 = DefaultHandler);
+PROVIDE(PWM3_3 = DefaultHandler);
+PROVIDE(PWM3_FAULT = DefaultHandler);
+PROVIDE(PWM4_0 = DefaultHandler);
+PROVIDE(PWM4_1 = DefaultHandler);
+PROVIDE(PWM4_2 = DefaultHandler);
+PROVIDE(PWM4_3 = DefaultHandler);
+PROVIDE(PWM4_FAULT = DefaultHandler);
+PROVIDE(CAN3 = DefaultHandler);
+PROVIDE(FLEXIO3 = DefaultHandler);
+PROVIDE(GPIO6_7_8_9 = DefaultHandler);
diff --git a/chips/imxrt1040/src/iomuxc.rs b/chips/imxrt1040/src/iomuxc.rs
new file mode 100644
index 0000000..60272ea
--- /dev/null
+++ b/chips/imxrt1040/src/iomuxc.rs
@@ -0,0 +1,287 @@
+//! I/O multiplexing and configuration.
+
+pub type RegisterBlock = imxrt_drivers_iomuxc_10xx::iomuxc::RegisterBlock<20, 124, 231>;
+
+pub use imxrt_drivers_iomuxc_10xx::iomuxc::{SELECT_INPUT, SW_MUX_CTL_PAD, SW_PAD_CTL_PAD};
+
+/// Indices for `sw_[pad|mux]_ctl_pad` registers.
+pub mod pad {
+    pub const GPIO_EMC_00: usize = 0;
+    pub const GPIO_EMC_01: usize = 1;
+    pub const GPIO_EMC_02: usize = 2;
+    pub const GPIO_EMC_03: usize = 3;
+    pub const GPIO_EMC_04: usize = 4;
+    pub const GPIO_EMC_05: usize = 5;
+    pub const GPIO_EMC_06: usize = 6;
+    pub const GPIO_EMC_07: usize = 7;
+    pub const GPIO_EMC_08: usize = 8;
+    pub const GPIO_EMC_09: usize = 9;
+    pub const GPIO_EMC_10: usize = 10;
+    pub const GPIO_EMC_11: usize = 11;
+    pub const GPIO_EMC_12: usize = 12;
+    pub const GPIO_EMC_13: usize = 13;
+    pub const GPIO_EMC_14: usize = 14;
+    pub const GPIO_EMC_15: usize = 15;
+    pub const GPIO_EMC_16: usize = 16;
+    pub const GPIO_EMC_17: usize = 17;
+    pub const GPIO_EMC_18: usize = 18;
+    pub const GPIO_EMC_19: usize = 19;
+    pub const GPIO_EMC_20: usize = 20;
+    pub const GPIO_EMC_21: usize = 21;
+    pub const GPIO_EMC_22: usize = 22;
+    pub const GPIO_EMC_23: usize = 23;
+    pub const GPIO_EMC_24: usize = 24;
+    pub const GPIO_EMC_25: usize = 25;
+    pub const GPIO_EMC_26: usize = 26;
+    pub const GPIO_EMC_27: usize = 27;
+    pub const GPIO_EMC_28: usize = 28;
+    pub const GPIO_EMC_29: usize = 29;
+    pub const GPIO_EMC_30: usize = 30;
+    pub const GPIO_EMC_31: usize = 31;
+    pub const GPIO_EMC_32: usize = 32;
+    pub const GPIO_EMC_33: usize = 33;
+    pub const GPIO_EMC_34: usize = 34;
+    pub const GPIO_EMC_35: usize = 35;
+    pub const GPIO_EMC_36: usize = 36;
+    pub const GPIO_EMC_37: usize = 37;
+    pub const GPIO_EMC_38: usize = 38;
+    pub const GPIO_EMC_39: usize = 39;
+    pub const GPIO_EMC_40: usize = 40;
+    pub const GPIO_EMC_41: usize = 41;
+    pub const GPIO_AD_B0_04: usize = 46;
+    pub const GPIO_AD_B0_05: usize = 47;
+    pub const GPIO_AD_B0_06: usize = 48;
+    pub const GPIO_AD_B0_07: usize = 49;
+    pub const GPIO_AD_B0_08: usize = 50;
+    pub const GPIO_AD_B0_09: usize = 51;
+    pub const GPIO_AD_B0_10: usize = 52;
+    pub const GPIO_AD_B0_11: usize = 53;
+    pub const GPIO_AD_B0_12: usize = 54;
+    pub const GPIO_AD_B0_13: usize = 55;
+    pub const GPIO_AD_B0_14: usize = 56;
+    pub const GPIO_AD_B0_15: usize = 57;
+    pub const GPIO_AD_B1_00: usize = 58;
+    pub const GPIO_AD_B1_01: usize = 59;
+    pub const GPIO_AD_B1_02: usize = 60;
+    pub const GPIO_AD_B1_03: usize = 61;
+    pub const GPIO_AD_B1_04: usize = 62;
+    pub const GPIO_AD_B1_05: usize = 63;
+    pub const GPIO_AD_B1_06: usize = 64;
+    pub const GPIO_AD_B1_07: usize = 65;
+    pub const GPIO_B0_00: usize = 74;
+    pub const GPIO_B0_01: usize = 75;
+    pub const GPIO_B0_02: usize = 76;
+    pub const GPIO_B0_03: usize = 77;
+    pub const GPIO_B0_04: usize = 78;
+    pub const GPIO_B0_05: usize = 79;
+    pub const GPIO_B0_06: usize = 80;
+    pub const GPIO_B0_07: usize = 81;
+    pub const GPIO_B0_08: usize = 82;
+    pub const GPIO_B0_09: usize = 83;
+    pub const GPIO_B0_10: usize = 84;
+    pub const GPIO_B0_11: usize = 85;
+    pub const GPIO_B0_12: usize = 86;
+    pub const GPIO_B0_13: usize = 87;
+    pub const GPIO_B0_14: usize = 88;
+    pub const GPIO_B0_15: usize = 89;
+    pub const GPIO_B1_00: usize = 90;
+    pub const GPIO_B1_01: usize = 91;
+    pub const GPIO_B1_02: usize = 92;
+    pub const GPIO_B1_03: usize = 93;
+    pub const GPIO_B1_04: usize = 94;
+    pub const GPIO_B1_05: usize = 95;
+    pub const GPIO_B1_06: usize = 96;
+    pub const GPIO_B1_07: usize = 97;
+    pub const GPIO_B1_08: usize = 98;
+    pub const GPIO_B1_09: usize = 99;
+    pub const GPIO_B1_10: usize = 100;
+    pub const GPIO_B1_11: usize = 101;
+    pub const GPIO_B1_12: usize = 102;
+    pub const GPIO_B1_13: usize = 103;
+    pub const GPIO_B1_14: usize = 104;
+    pub const GPIO_B1_15: usize = 105;
+    pub const GPIO_SD_B0_00: usize = 106;
+    pub const GPIO_SD_B0_01: usize = 107;
+    pub const GPIO_SD_B0_02: usize = 108;
+    pub const GPIO_SD_B0_03: usize = 109;
+    pub const GPIO_SD_B0_04: usize = 110;
+    pub const GPIO_SD_B0_05: usize = 111;
+    pub const GPIO_SD_B1_00: usize = 112;
+    pub const GPIO_SD_B1_01: usize = 113;
+    pub const GPIO_SD_B1_02: usize = 114;
+    pub const GPIO_SD_B1_03: usize = 115;
+    pub const GPIO_SD_B1_04: usize = 116;
+    pub const GPIO_SD_B1_05: usize = 117;
+    pub const GPIO_SD_B1_06: usize = 118;
+    pub const GPIO_SD_B1_07: usize = 119;
+    pub const GPIO_SD_B1_08: usize = 120;
+    pub const GPIO_SD_B1_09: usize = 121;
+    pub const GPIO_SD_B1_10: usize = 122;
+    pub const GPIO_SD_B1_11: usize = 123;
+}
+
+/// Indices for `select_input` registers.
+pub mod select_input {
+    pub const ANATOP_USB_OTG1_ID: usize = 0;
+    pub const CCM_PMIC_READY: usize = 2;
+    pub const ENET_IPG_CLK_RMII: usize = 14;
+    pub const ENET_MDIO: usize = 15;
+    pub const ENET0_RXDATA: usize = 16;
+    pub const ENET1_RXDATA: usize = 17;
+    pub const ENET_RXEN: usize = 18;
+    pub const ENET_RXERR: usize = 19;
+    pub const ENET0_TIMER: usize = 20;
+    pub const ENET_TXCLK: usize = 21;
+    pub const FLEXCAN1_RX: usize = 22;
+    pub const FLEXCAN2_RX: usize = 23;
+    pub const FLEXPWM1_PWMA3: usize = 24;
+    pub const FLEXPWM1_PWMA0: usize = 25;
+    pub const FLEXPWM1_PWMA1: usize = 26;
+    pub const FLEXPWM1_PWMA2: usize = 27;
+    pub const FLEXPWM1_PWMB3: usize = 28;
+    pub const FLEXPWM1_PWMB0: usize = 29;
+    pub const FLEXPWM1_PWMB1: usize = 30;
+    pub const FLEXPWM1_PWMB2: usize = 31;
+    pub const FLEXPWM2_PWMA3: usize = 32;
+    pub const FLEXPWM2_PWMA0: usize = 33;
+    pub const FLEXPWM2_PWMA1: usize = 34;
+    pub const FLEXPWM2_PWMA2: usize = 35;
+    pub const FLEXPWM2_PWMB3: usize = 36;
+    pub const FLEXPWM2_PWMB0: usize = 37;
+    pub const FLEXPWM2_PWMB1: usize = 38;
+    pub const FLEXPWM2_PWMB2: usize = 39;
+    pub const FLEXPWM4_PWMA0: usize = 40;
+    pub const FLEXPWM4_PWMA1: usize = 41;
+    pub const FLEXPWM4_PWMA2: usize = 42;
+    pub const FLEXPWM4_PWMA3: usize = 43;
+    pub const FLEXSPIA_DQS: usize = 44;
+    pub const FLEXSPIA_DATA0: usize = 45;
+    pub const FLEXSPIA_DATA1: usize = 46;
+    pub const FLEXSPIA_DATA2: usize = 47;
+    pub const FLEXSPIA_DATA3: usize = 48;
+    pub const FLEXSPIB_DATA0: usize = 49;
+    pub const FLEXSPIB_DATA1: usize = 50;
+    pub const FLEXSPIB_DATA2: usize = 51;
+    pub const FLEXSPIB_DATA3: usize = 52;
+    pub const FLEXSPIA_SCK: usize = 53;
+    pub const LPI2C1_SCL: usize = 54;
+    pub const LPI2C1_SDA: usize = 55;
+    pub const LPI2C2_SCL: usize = 56;
+    pub const LPI2C2_SDA: usize = 57;
+    pub const LPI2C3_SCL: usize = 58;
+    pub const LPI2C3_SDA: usize = 59;
+    pub const LPI2C4_SCL: usize = 60;
+    pub const LPI2C4_SDA: usize = 61;
+    pub const LPSPI1_PCS0: usize = 62;
+    pub const LPSPI1_SCK: usize = 63;
+    pub const LPSPI1_SDI: usize = 64;
+    pub const LPSPI1_SDO: usize = 65;
+    pub const LPSPI2_PCS0: usize = 66;
+    pub const LPSPI2_SCK: usize = 67;
+    pub const LPSPI2_SDI: usize = 68;
+    pub const LPSPI2_SDO: usize = 69;
+    pub const LPSPI3_PCS0: usize = 74;
+    pub const LPSPI3_SCK: usize = 75;
+    pub const LPSPI3_SDI: usize = 76;
+    pub const LPSPI3_SDO: usize = 77;
+    pub const LPUART2_RX: usize = 78;
+    pub const LPUART2_TX: usize = 79;
+    pub const LPUART3_CTS_B: usize = 80;
+    pub const LPUART3_RX: usize = 81;
+    pub const LPUART3_TX: usize = 82;
+    pub const LPUART4_RX: usize = 83;
+    pub const LPUART4_TX: usize = 84;
+    pub const LPUART5_RX: usize = 85;
+    pub const LPUART5_TX: usize = 86;
+    pub const LPUART6_RX: usize = 87;
+    pub const LPUART6_TX: usize = 88;
+    pub const LPUART7_RX: usize = 89;
+    pub const LPUART7_TX: usize = 90;
+    pub const LPUART8_RX: usize = 91;
+    pub const LPUART8_TX: usize = 92;
+    pub const NMI: usize = 93;
+    pub const QTIMER2_TIMER0: usize = 94;
+    pub const QTIMER2_TIMER1: usize = 95;
+    pub const QTIMER2_TIMER2: usize = 96;
+    pub const QTIMER2_TIMER3: usize = 97;
+    pub const QTIMER3_TIMER0: usize = 98;
+    pub const QTIMER3_TIMER1: usize = 99;
+    pub const QTIMER3_TIMER2: usize = 100;
+    pub const QTIMER3_TIMER3: usize = 101;
+    pub const SAI1_MCLK2: usize = 102;
+    pub const SAI1_RX_BCLK: usize = 103;
+    pub const SAI1_RX_DATA0: usize = 104;
+    pub const SAI1_RX_DATA1: usize = 105;
+    pub const SAI1_RX_DATA2: usize = 106;
+    pub const SAI1_RX_DATA3: usize = 107;
+    pub const SAI1_RX_SYNC: usize = 108;
+    pub const SAI1_TX_BCLK: usize = 109;
+    pub const SAI1_TX_SYNC: usize = 110;
+    pub const SAI2_MCLK2: usize = 111;
+    pub const SAI2_RX_BCLK: usize = 112;
+    pub const SAI2_RX_DATA0: usize = 113;
+    pub const SAI2_RX_SYNC: usize = 114;
+    pub const SAI2_TX_BCLK: usize = 115;
+    pub const SAI2_TX_SYNC: usize = 116;
+    pub const SPDIF_IN: usize = 117;
+    pub const USB_OTG1_OC: usize = 119;
+    pub const USDHC1_CD_B: usize = 120;
+    pub const USDHC1_WP: usize = 121;
+    pub const USDHC2_CLK: usize = 122;
+    pub const USDHC2_CD_B: usize = 123;
+    pub const USDHC2_CMD: usize = 124;
+    pub const USDHC2_DATA0: usize = 125;
+    pub const USDHC2_DATA1: usize = 126;
+    pub const USDHC2_DATA2: usize = 127;
+    pub const USDHC2_DATA3: usize = 128;
+    pub const USDHC2_DATA4: usize = 129;
+    pub const USDHC2_DATA5: usize = 130;
+    pub const USDHC2_DATA6: usize = 131;
+    pub const USDHC2_DATA7: usize = 132;
+    pub const USDHC2_WP: usize = 133;
+    pub const XBAR1_IN02: usize = 134;
+    pub const XBAR1_IN03: usize = 135;
+    pub const XBAR1_IN04: usize = 136;
+    pub const XBAR1_IN05: usize = 137;
+    pub const XBAR1_IN06: usize = 138;
+    pub const XBAR1_IN07: usize = 139;
+    pub const XBAR1_IN08: usize = 140;
+    pub const XBAR1_IN09: usize = 141;
+    pub const XBAR1_IN17: usize = 142;
+    pub const XBAR1_IN18: usize = 143;
+    pub const XBAR1_IN20: usize = 144;
+    pub const XBAR1_IN22: usize = 145;
+    pub const XBAR1_IN23: usize = 146;
+    pub const XBAR1_IN24: usize = 147;
+    pub const XBAR1_IN14: usize = 148;
+    pub const XBAR1_IN15: usize = 149;
+    pub const XBAR1_IN16: usize = 150;
+    pub const XBAR1_IN25: usize = 151;
+    pub const XBAR1_IN19: usize = 152;
+    pub const XBAR1_IN21: usize = 153;
+    pub const FLEXSPI2_IPP_IND_DQS_FA: usize = 206;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT0: usize = 207;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT1: usize = 208;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT2: usize = 209;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT3: usize = 210;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT0: usize = 211;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT1: usize = 212;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT2: usize = 213;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT3: usize = 214;
+    pub const FLEXSPI2_IPP_IND_SCK_FA: usize = 215;
+    pub const FLEXSPI2_IPP_IND_SCK_FB: usize = 216;
+    pub const GPT1_IPP_IND_CAPIN1: usize = 217;
+    pub const GPT1_IPP_IND_CAPIN2: usize = 218;
+    pub const GPT1_IPP_IND_CLKIN: usize = 219;
+    pub const GPT2_IPP_IND_CAPIN1: usize = 220;
+    pub const GPT2_IPP_IND_CAPIN2: usize = 221;
+    pub const GPT2_IPP_IND_CLKIN: usize = 222;
+    pub const SAI3_IPG_CLK_SAI_MCLK_S: usize = 223;
+    pub const SAI3_IPP_IND_SAI_RXBCLK: usize = 224;
+    pub const SAI3_IPP_IND_SAI_RXDATA_S: usize = 225;
+    pub const SAI3_IPP_IND_SAI_RXSYNC: usize = 226;
+    pub const SAI3_IPP_IND_SAI_TXBCLK: usize = 227;
+    pub const SAI3_IPP_IND_SAI_TXSYNC: usize = 228;
+    pub const SEMC_I_IPP_IND_DQS4: usize = 229;
+    pub const CANFD_IPP_IND_CANRX: usize = 230;
+}
diff --git a/chips/imxrt1040/src/lib.rs b/chips/imxrt1040/src/lib.rs
new file mode 100644
index 0000000..56733b5
--- /dev/null
+++ b/chips/imxrt1040/src/lib.rs
@@ -0,0 +1,105 @@
+//! Drivers for iMXRT1040 MCUs.
+
+#![no_std]
+
+pub use ral_registers::{Instance, modify_reg, read_reg, write_reg};
+
+mod rt;
+pub use rt::*;
+
+pub mod iomuxc;
+
+pub mod iomuxc_gpr {
+    pub type RegisterBlock = imxrt_drivers_iomuxc_10xx::iomuxc_gpr::RegisterBlock<35>;
+    pub use imxrt_drivers_iomuxc_10xx::iomuxc_gpr::GPR;
+}
+
+/// Clock control module.
+pub mod ccm {
+    pub use imxrt_drivers_ccm_10xx::ahb::pll1::*;
+
+    pub use imxrt_drivers_ccm_10xx::ccm::{
+        CCM, LowPowerMode, ahb_clk, clock_gate, flexspi1_clk_axi_semc as flexspi1_clk, ipg_clk,
+        low_power_mode, lpi2c_clk, lpspi_clk, perclk_clk, set_low_power_mode, uart_clk,
+    };
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::{CCM_ANALOG, pll2, pll3};
+
+    pub use imxrt_drivers_ccm_10xx::ccm::{
+        arm_divider, periph_clk2, pre_periph_clk_pll1 as pre_periph_clk,
+    };
+
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::{pll1, pll6};
+
+    pub mod gates {
+        use super::clock_gate::Locator::{self, *};
+
+        pub const LPSPI1: Locator = Ccgr1Cg00;
+        pub const DMA: Locator = Ccgr5Cg03;
+        pub const PIT: Locator = Ccgr1Cg06;
+        pub const FLEXSPI1: Locator = Ccgr6Cg05;
+    }
+    pub use imxrt_drivers_ccm_10xx::ral;
+}
+
+pub mod dma {
+    pub use imxrt_drivers_edma::dma::edma as controller;
+    pub use imxrt_drivers_edma::dmamux as mux;
+    pub use imxrt_drivers_edma::edma as channel;
+    pub use imxrt_drivers_edma::element;
+
+    pub mod events {
+        use core::num::NonZero;
+
+        pub const LPSPI_RX: NonZero<u8> = NonZero::new(13).unwrap();
+        pub const LPSPI_TX: NonZero<u8> = NonZero::new(14).unwrap();
+    }
+}
+
+pub use imxrt_drivers_dcdc as dcdc;
+pub use imxrt_drivers_enet as enet;
+pub use imxrt_drivers_flexspi as flexspi;
+pub use imxrt_drivers_gpio as gpio;
+pub use imxrt_drivers_lpspi as lpspi;
+pub use imxrt_drivers_pit as pit;
+pub use imxrt_drivers_rtwdog as rtwdog;
+
+/// Peripheral instances.
+pub mod instances {
+    ral_registers::instances! {
+        // Safety: The reference manual confirms there are register
+        // blocks at this address matching this shape.
+        unsafe {
+            /// Access CCM registers.
+            pub ccm<imxrt_drivers_ccm_10xx::ral::ccm::RegisterBlock> = 0x400F_C000;
+            /// Access CCM\_ANALOG registers.
+            pub ccm_analog<imxrt_drivers_ccm_10xx::ral::ccm_analog::RegisterBlock> = 0x400D_8000;
+
+            pub dcdc<crate::dcdc::RegisterBlock> = 0x4008_0000;
+
+            pub gpio1<crate::gpio::RegisterBlock> = 0x401b_8000;
+            pub gpio2<crate::gpio::RegisterBlock> = 0x401b_c000;
+            pub gpio3<crate::gpio::RegisterBlock> = 0x401C_0000;
+            pub gpio4<crate::gpio::RegisterBlock> = 0x401C_4000;
+            pub gpio5<crate::gpio::RegisterBlock> = 0x400C_0000;
+
+            pub iomuxc<crate::iomuxc::RegisterBlock> = 0x401F_8000;
+            pub iomuxc_gpr<crate::iomuxc_gpr::RegisterBlock> = 0x400A_C000;
+
+            pub enet<crate::enet::RegisterBlock> = 0x402D_8000;
+
+            pub flexspi1<crate::flexspi::RegisterBlock> = 0x402A_8000;
+            pub flexspi2<crate::flexspi::RegisterBlock> = 0x402A_4000;
+
+            pub pit<crate::pit::RegisterBlock> = 0x4008_4000;
+
+            pub lpspi1<crate::lpspi::RegisterBlock> = 0x4039_4000;
+            pub lpspi2<crate::lpspi::RegisterBlock> = 0x4039_8000;
+            pub lpspi3<crate::lpspi::RegisterBlock> = 0x403A_0000;
+
+            pub dma<crate::dma::controller::RegisterBlock> = 0x400E_8000;
+            pub dmamux<crate::dma::mux::RegisterBlock> = 0x400E_C000;
+
+            pub wdog3<crate::rtwdog::RegisterBlock> = 0x400B_C000;
+        }
+    }
+}
diff --git a/chips/imxrt1040/src/rt.rs b/chips/imxrt1040/src/rt.rs
new file mode 100644
index 0000000..0ee8798
--- /dev/null
+++ b/chips/imxrt1040/src/rt.rs
@@ -0,0 +1,703 @@
+#![allow(non_camel_case_types)]
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - DMA0_DMA16"]
+    DMA0_DMA16 = 0,
+    #[doc = "1 - DMA1_DMA17"]
+    DMA1_DMA17 = 1,
+    #[doc = "2 - DMA2_DMA18"]
+    DMA2_DMA18 = 2,
+    #[doc = "3 - DMA3_DMA19"]
+    DMA3_DMA19 = 3,
+    #[doc = "4 - DMA4_DMA20"]
+    DMA4_DMA20 = 4,
+    #[doc = "5 - DMA5_DMA21"]
+    DMA5_DMA21 = 5,
+    #[doc = "6 - DMA6_DMA22"]
+    DMA6_DMA22 = 6,
+    #[doc = "7 - DMA7_DMA23"]
+    DMA7_DMA23 = 7,
+    #[doc = "8 - DMA8_DMA24"]
+    DMA8_DMA24 = 8,
+    #[doc = "9 - DMA9_DMA25"]
+    DMA9_DMA25 = 9,
+    #[doc = "10 - DMA10_DMA26"]
+    DMA10_DMA26 = 10,
+    #[doc = "11 - DMA11_DMA27"]
+    DMA11_DMA27 = 11,
+    #[doc = "12 - DMA12_DMA28"]
+    DMA12_DMA28 = 12,
+    #[doc = "13 - DMA13_DMA29"]
+    DMA13_DMA29 = 13,
+    #[doc = "14 - DMA14_DMA30"]
+    DMA14_DMA30 = 14,
+    #[doc = "15 - DMA15_DMA31"]
+    DMA15_DMA31 = 15,
+    #[doc = "16 - DMA_ERROR"]
+    DMA_ERROR = 16,
+    #[doc = "20 - LPUART1"]
+    LPUART1 = 20,
+    #[doc = "21 - LPUART2"]
+    LPUART2 = 21,
+    #[doc = "22 - LPUART3"]
+    LPUART3 = 22,
+    #[doc = "23 - LPUART4"]
+    LPUART4 = 23,
+    #[doc = "24 - LPUART5"]
+    LPUART5 = 24,
+    #[doc = "25 - LPUART6"]
+    LPUART6 = 25,
+    #[doc = "26 - LPUART7"]
+    LPUART7 = 26,
+    #[doc = "27 - LPUART8"]
+    LPUART8 = 27,
+    #[doc = "28 - LPI2C1"]
+    LPI2C1 = 28,
+    #[doc = "29 - LPI2C2"]
+    LPI2C2 = 29,
+    #[doc = "30 - LPI2C3"]
+    LPI2C3 = 30,
+    #[doc = "31 - LPI2C4"]
+    LPI2C4 = 31,
+    #[doc = "32 - LPSPI1"]
+    LPSPI1 = 32,
+    #[doc = "33 - LPSPI2"]
+    LPSPI2 = 33,
+    #[doc = "35 - LPSPI3"]
+    LPSPI3 = 35,
+    #[doc = "36 - CAN1"]
+    CAN1 = 36,
+    #[doc = "37 - CAN2"]
+    CAN2 = 37,
+    #[doc = "38 - FLEXRAM"]
+    FLEXRAM = 38,
+    #[doc = "41 - GPR (aka \"GPC\") interrupt request"]
+    GPR_IRQ = 41,
+    #[doc = "42 - LCDIF"]
+    LCDIF = 42,
+    #[doc = "44 - PXP"]
+    PXP = 44,
+    #[doc = "45 - WDOG2"]
+    WDOG2 = 45,
+    #[doc = "46 - SNVS_HP_WRAPPER"]
+    SNVS_HP_WRAPPER = 46,
+    #[doc = "47 - SNVS_HP_WRAPPER_TZ"]
+    SNVS_HP_WRAPPER_TZ = 47,
+    #[doc = "48 - SNVS_LP_WRAPPER"]
+    SNVS_LP_WRAPPER = 48,
+    #[doc = "49 - CSU"]
+    CSU = 49,
+    #[doc = "50 - DCP"]
+    DCP = 50,
+    #[doc = "51 - DCP_VMI"]
+    DCP_VMI = 51,
+    #[doc = "53 - TRNG"]
+    TRNG = 53,
+    #[doc = "55 - BEE"]
+    BEE = 55,
+    #[doc = "56 - SAI1"]
+    SAI1 = 56,
+    #[doc = "57 - SAI2"]
+    SAI2 = 57,
+    #[doc = "58 - SAI3_RX"]
+    SAI3_RX = 58,
+    #[doc = "59 - SAI3_TX"]
+    SAI3_TX = 59,
+    #[doc = "60 - SPDIF"]
+    SPDIF = 60,
+    #[doc = "61 - PMU_EVENT"]
+    PMU_EVENT = 61,
+    #[doc = "63 - TEMP_LOW_HIGH"]
+    TEMP_LOW_HIGH = 63,
+    #[doc = "64 - TEMP_PANIC"]
+    TEMP_PANIC = 64,
+    #[doc = "65 - USB_PHY1"]
+    USB_PHY1 = 65,
+    #[doc = "67 - ADC1"]
+    ADC1 = 67,
+    #[doc = "68 - ADC2"]
+    ADC2 = 68,
+    #[doc = "69 - DCDC"]
+    DCDC = 69,
+    #[doc = "72 - GPIO1_INT0"]
+    GPIO1_INT0 = 72,
+    #[doc = "73 - GPIO1_INT1"]
+    GPIO1_INT1 = 73,
+    #[doc = "74 - GPIO1_INT2"]
+    GPIO1_INT2 = 74,
+    #[doc = "75 - GPIO1_INT3"]
+    GPIO1_INT3 = 75,
+    #[doc = "76 - GPIO1_INT4"]
+    GPIO1_INT4 = 76,
+    #[doc = "77 - GPIO1_INT5"]
+    GPIO1_INT5 = 77,
+    #[doc = "78 - GPIO1_INT6"]
+    GPIO1_INT6 = 78,
+    #[doc = "79 - GPIO1_INT7"]
+    GPIO1_INT7 = 79,
+    #[doc = "80 - GPIO1_COMBINED_0_15"]
+    GPIO1_COMBINED_0_15 = 80,
+    #[doc = "81 - GPIO1_COMBINED_16_31"]
+    GPIO1_COMBINED_16_31 = 81,
+    #[doc = "82 - GPIO2_COMBINED_0_15"]
+    GPIO2_COMBINED_0_15 = 82,
+    #[doc = "83 - GPIO2_COMBINED_16_31"]
+    GPIO2_COMBINED_16_31 = 83,
+    #[doc = "84 - GPIO3_COMBINED_0_15"]
+    GPIO3_COMBINED_0_15 = 84,
+    #[doc = "85 - GPIO3_COMBINED_16_31"]
+    GPIO3_COMBINED_16_31 = 85,
+    #[doc = "86 - GPIO4_COMBINED_0_15"]
+    GPIO4_COMBINED_0_15 = 86,
+    #[doc = "87 - GPIO4_COMBINED_16_31"]
+    GPIO4_COMBINED_16_31 = 87,
+    #[doc = "88 - GPIO5_COMBINED_0_15"]
+    GPIO5_COMBINED_0_15 = 88,
+    #[doc = "89 - GPIO5_COMBINED_16_31"]
+    GPIO5_COMBINED_16_31 = 89,
+    #[doc = "90 - FLEXIO1"]
+    FLEXIO1 = 90,
+    #[doc = "91 - FLEXIO2"]
+    FLEXIO2 = 91,
+    #[doc = "92 - WDOG1"]
+    WDOG1 = 92,
+    #[doc = "93 - RTWDOG"]
+    RTWDOG = 93,
+    #[doc = "94 - EWM"]
+    EWM = 94,
+    #[doc = "95 - CCM_1"]
+    CCM_1 = 95,
+    #[doc = "96 - CCM_2"]
+    CCM_2 = 96,
+    #[doc = "97 - GPC"]
+    GPC = 97,
+    #[doc = "98 - SRC"]
+    SRC = 98,
+    #[doc = "100 - GPT1"]
+    GPT1 = 100,
+    #[doc = "101 - GPT2"]
+    GPT2 = 101,
+    #[doc = "102 - PWM1_0"]
+    PWM1_0 = 102,
+    #[doc = "103 - PWM1_1"]
+    PWM1_1 = 103,
+    #[doc = "104 - PWM1_2"]
+    PWM1_2 = 104,
+    #[doc = "105 - PWM1_3"]
+    PWM1_3 = 105,
+    #[doc = "106 - PWM1_FAULT"]
+    PWM1_FAULT = 106,
+    #[doc = "107 - FLEXSPI2"]
+    FLEXSPI2 = 107,
+    #[doc = "108 - FLEXSPI"]
+    FLEXSPI = 108,
+    #[doc = "109 - SEMC"]
+    SEMC = 109,
+    #[doc = "110 - USDHC1"]
+    USDHC1 = 110,
+    #[doc = "111 - USDHC2"]
+    USDHC2 = 111,
+    #[doc = "113 - USB_OTG1"]
+    USB_OTG1 = 113,
+    #[doc = "114 - ENET"]
+    ENET = 114,
+    #[doc = "115 - ENET_1588_TIMER"]
+    ENET_1588_TIMER = 115,
+    #[doc = "116 - XBAR1_IRQ_0_1"]
+    XBAR1_IRQ_0_1 = 116,
+    #[doc = "117 - XBAR1_IRQ_2_3"]
+    XBAR1_IRQ_2_3 = 117,
+    #[doc = "118 - ADC_ETC_IRQ0"]
+    ADC_ETC_IRQ0 = 118,
+    #[doc = "119 - ADC_ETC_IRQ1"]
+    ADC_ETC_IRQ1 = 119,
+    #[doc = "120 - ADC_ETC_IRQ2"]
+    ADC_ETC_IRQ2 = 120,
+    #[doc = "121 - ADC_ETC_ERROR_IRQ"]
+    ADC_ETC_ERROR_IRQ = 121,
+    #[doc = "122 - PIT"]
+    PIT = 122,
+    #[doc = "123 - ACMP1"]
+    ACMP1 = 123,
+    #[doc = "124 - ACMP2"]
+    ACMP2 = 124,
+    #[doc = "125 - ACMP3"]
+    ACMP3 = 125,
+    #[doc = "126 - ACMP4"]
+    ACMP4 = 126,
+    #[doc = "129 - ENC1"]
+    ENC1 = 129,
+    #[doc = "130 - ENC2"]
+    ENC2 = 130,
+    #[doc = "131 - ENC3"]
+    ENC3 = 131,
+    #[doc = "132 - ENC4"]
+    ENC4 = 132,
+    #[doc = "133 - TMR1"]
+    TMR1 = 133,
+    #[doc = "134 - TMR2"]
+    TMR2 = 134,
+    #[doc = "135 - TMR3"]
+    TMR3 = 135,
+    #[doc = "136 - TMR4"]
+    TMR4 = 136,
+    #[doc = "137 - PWM2_0"]
+    PWM2_0 = 137,
+    #[doc = "138 - PWM2_1"]
+    PWM2_1 = 138,
+    #[doc = "139 - PWM2_2"]
+    PWM2_2 = 139,
+    #[doc = "140 - PWM2_3"]
+    PWM2_3 = 140,
+    #[doc = "141 - PWM2_FAULT"]
+    PWM2_FAULT = 141,
+    #[doc = "142 - PWM3_0"]
+    PWM3_0 = 142,
+    #[doc = "143 - PWM3_1"]
+    PWM3_1 = 143,
+    #[doc = "144 - PWM3_2"]
+    PWM3_2 = 144,
+    #[doc = "145 - PWM3_3"]
+    PWM3_3 = 145,
+    #[doc = "146 - PWM3_FAULT"]
+    PWM3_FAULT = 146,
+    #[doc = "147 - PWM4_0"]
+    PWM4_0 = 147,
+    #[doc = "148 - PWM4_1"]
+    PWM4_1 = 148,
+    #[doc = "149 - PWM4_2"]
+    PWM4_2 = 149,
+    #[doc = "150 - PWM4_3"]
+    PWM4_3 = 150,
+    #[doc = "151 - PWM4_FAULT"]
+    PWM4_FAULT = 151,
+    #[doc = "154 - CAN3"]
+    CAN3 = 154,
+    #[doc = "156 - FLEXIO3"]
+    FLEXIO3 = 156,
+    #[doc = "157 - GPIO6_7_8_9"]
+    GPIO6_7_8_9 = 157,
+}
+pub type interrupt = Interrupt;
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+
+mod _vectors {
+    unsafe extern "C" {
+        fn DMA0_DMA16();
+        fn DMA1_DMA17();
+        fn DMA2_DMA18();
+        fn DMA3_DMA19();
+        fn DMA4_DMA20();
+        fn DMA5_DMA21();
+        fn DMA6_DMA22();
+        fn DMA7_DMA23();
+        fn DMA8_DMA24();
+        fn DMA9_DMA25();
+        fn DMA10_DMA26();
+        fn DMA11_DMA27();
+        fn DMA12_DMA28();
+        fn DMA13_DMA29();
+        fn DMA14_DMA30();
+        fn DMA15_DMA31();
+        fn DMA_ERROR();
+        fn LPUART1();
+        fn LPUART2();
+        fn LPUART3();
+        fn LPUART4();
+        fn LPUART5();
+        fn LPUART6();
+        fn LPUART7();
+        fn LPUART8();
+        fn LPI2C1();
+        fn LPI2C2();
+        fn LPI2C3();
+        fn LPI2C4();
+        fn LPSPI1();
+        fn LPSPI2();
+        fn LPSPI3();
+        fn CAN1();
+        fn CAN2();
+        fn FLEXRAM();
+        fn GPR_IRQ();
+        fn LCDIF();
+        fn PXP();
+        fn WDOG2();
+        fn SNVS_HP_WRAPPER();
+        fn SNVS_HP_WRAPPER_TZ();
+        fn SNVS_LP_WRAPPER();
+        fn CSU();
+        fn DCP();
+        fn DCP_VMI();
+        fn TRNG();
+        fn BEE();
+        fn SAI1();
+        fn SAI2();
+        fn SAI3_RX();
+        fn SAI3_TX();
+        fn SPDIF();
+        fn PMU_EVENT();
+        fn TEMP_LOW_HIGH();
+        fn TEMP_PANIC();
+        fn USB_PHY1();
+        fn ADC1();
+        fn ADC2();
+        fn DCDC();
+        fn GPIO1_INT0();
+        fn GPIO1_INT1();
+        fn GPIO1_INT2();
+        fn GPIO1_INT3();
+        fn GPIO1_INT4();
+        fn GPIO1_INT5();
+        fn GPIO1_INT6();
+        fn GPIO1_INT7();
+        fn GPIO1_COMBINED_0_15();
+        fn GPIO1_COMBINED_16_31();
+        fn GPIO2_COMBINED_0_15();
+        fn GPIO2_COMBINED_16_31();
+        fn GPIO3_COMBINED_0_15();
+        fn GPIO3_COMBINED_16_31();
+        fn GPIO4_COMBINED_0_15();
+        fn GPIO4_COMBINED_16_31();
+        fn GPIO5_COMBINED_0_15();
+        fn GPIO5_COMBINED_16_31();
+        fn FLEXIO1();
+        fn FLEXIO2();
+        fn WDOG1();
+        fn RTWDOG();
+        fn EWM();
+        fn CCM_1();
+        fn CCM_2();
+        fn GPC();
+        fn SRC();
+        fn GPT1();
+        fn GPT2();
+        fn PWM1_0();
+        fn PWM1_1();
+        fn PWM1_2();
+        fn PWM1_3();
+        fn PWM1_FAULT();
+        fn FLEXSPI2();
+        fn FLEXSPI();
+        fn SEMC();
+        fn USDHC1();
+        fn USDHC2();
+        fn USB_OTG1();
+        fn ENET();
+        fn ENET_1588_TIMER();
+        fn XBAR1_IRQ_0_1();
+        fn XBAR1_IRQ_2_3();
+        fn ADC_ETC_IRQ0();
+        fn ADC_ETC_IRQ1();
+        fn ADC_ETC_IRQ2();
+        fn ADC_ETC_ERROR_IRQ();
+        fn PIT();
+        fn ACMP1();
+        fn ACMP2();
+        fn ACMP3();
+        fn ACMP4();
+        fn ENC1();
+        fn ENC2();
+        fn ENC3();
+        fn ENC4();
+        fn TMR1();
+        fn TMR2();
+        fn TMR3();
+        fn TMR4();
+        fn PWM2_0();
+        fn PWM2_1();
+        fn PWM2_2();
+        fn PWM2_3();
+        fn PWM2_FAULT();
+        fn PWM3_0();
+        fn PWM3_1();
+        fn PWM3_2();
+        fn PWM3_3();
+        fn PWM3_FAULT();
+        fn PWM4_0();
+        fn PWM4_1();
+        fn PWM4_2();
+        fn PWM4_3();
+        fn PWM4_FAULT();
+        fn CAN3();
+        fn FLEXIO3();
+        fn GPIO6_7_8_9();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".vector_table.interrupts"))]
+    #[unsafe(no_mangle)]
+    pub static __INTERRUPTS: [Vector; 158] = [
+        Vector {
+            _handler: DMA0_DMA16,
+        },
+        Vector {
+            _handler: DMA1_DMA17,
+        },
+        Vector {
+            _handler: DMA2_DMA18,
+        },
+        Vector {
+            _handler: DMA3_DMA19,
+        },
+        Vector {
+            _handler: DMA4_DMA20,
+        },
+        Vector {
+            _handler: DMA5_DMA21,
+        },
+        Vector {
+            _handler: DMA6_DMA22,
+        },
+        Vector {
+            _handler: DMA7_DMA23,
+        },
+        Vector {
+            _handler: DMA8_DMA24,
+        },
+        Vector {
+            _handler: DMA9_DMA25,
+        },
+        Vector {
+            _handler: DMA10_DMA26,
+        },
+        Vector {
+            _handler: DMA11_DMA27,
+        },
+        Vector {
+            _handler: DMA12_DMA28,
+        },
+        Vector {
+            _handler: DMA13_DMA29,
+        },
+        Vector {
+            _handler: DMA14_DMA30,
+        },
+        Vector {
+            _handler: DMA15_DMA31,
+        },
+        Vector {
+            _handler: DMA_ERROR,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: LPUART2 },
+        Vector { _handler: LPUART3 },
+        Vector { _handler: LPUART4 },
+        Vector { _handler: LPUART5 },
+        Vector { _handler: LPUART6 },
+        Vector { _handler: LPUART7 },
+        Vector { _handler: LPUART8 },
+        Vector { _handler: LPI2C1 },
+        Vector { _handler: LPI2C2 },
+        Vector { _handler: LPI2C3 },
+        Vector { _handler: LPI2C4 },
+        Vector { _handler: LPSPI1 },
+        Vector { _handler: LPSPI2 },
+        Vector { _reserved: 0 },
+        Vector { _handler: LPSPI3 },
+        Vector { _handler: CAN1 },
+        Vector { _handler: CAN2 },
+        Vector { _handler: FLEXRAM },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: GPR_IRQ },
+        Vector { _handler: LCDIF },
+        Vector { _reserved: 0 },
+        Vector { _handler: PXP },
+        Vector { _handler: WDOG2 },
+        Vector {
+            _handler: SNVS_HP_WRAPPER,
+        },
+        Vector {
+            _handler: SNVS_HP_WRAPPER_TZ,
+        },
+        Vector {
+            _handler: SNVS_LP_WRAPPER,
+        },
+        Vector { _handler: CSU },
+        Vector { _handler: DCP },
+        Vector { _handler: DCP_VMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: TRNG },
+        Vector { _reserved: 0 },
+        Vector { _handler: BEE },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SAI3_RX },
+        Vector { _handler: SAI3_TX },
+        Vector { _handler: SPDIF },
+        Vector {
+            _handler: PMU_EVENT,
+        },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: TEMP_LOW_HIGH,
+        },
+        Vector {
+            _handler: TEMP_PANIC,
+        },
+        Vector { _handler: USB_PHY1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: ADC1 },
+        Vector { _handler: ADC2 },
+        Vector { _handler: DCDC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: GPIO1_INT0,
+        },
+        Vector {
+            _handler: GPIO1_INT1,
+        },
+        Vector {
+            _handler: GPIO1_INT2,
+        },
+        Vector {
+            _handler: GPIO1_INT3,
+        },
+        Vector {
+            _handler: GPIO1_INT4,
+        },
+        Vector {
+            _handler: GPIO1_INT5,
+        },
+        Vector {
+            _handler: GPIO1_INT6,
+        },
+        Vector {
+            _handler: GPIO1_INT7,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_16_31,
+        },
+        Vector { _handler: FLEXIO1 },
+        Vector { _handler: FLEXIO2 },
+        Vector { _handler: WDOG1 },
+        Vector { _handler: RTWDOG },
+        Vector { _handler: EWM },
+        Vector { _handler: CCM_1 },
+        Vector { _handler: CCM_2 },
+        Vector { _handler: GPC },
+        Vector { _handler: SRC },
+        Vector { _reserved: 0 },
+        Vector { _handler: GPT1 },
+        Vector { _handler: GPT2 },
+        Vector { _handler: PWM1_0 },
+        Vector { _handler: PWM1_1 },
+        Vector { _handler: PWM1_2 },
+        Vector { _handler: PWM1_3 },
+        Vector {
+            _handler: PWM1_FAULT,
+        },
+        Vector { _handler: FLEXSPI2 },
+        Vector { _handler: FLEXSPI },
+        Vector { _handler: SEMC },
+        Vector { _handler: USDHC1 },
+        Vector { _handler: USDHC2 },
+        Vector { _reserved: 0 },
+        Vector { _handler: USB_OTG1 },
+        Vector { _handler: ENET },
+        Vector {
+            _handler: ENET_1588_TIMER,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_0_1,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_2_3,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ0,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ1,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ2,
+        },
+        Vector {
+            _handler: ADC_ETC_ERROR_IRQ,
+        },
+        Vector { _handler: PIT },
+        Vector { _handler: ACMP1 },
+        Vector { _handler: ACMP2 },
+        Vector { _handler: ACMP3 },
+        Vector { _handler: ACMP4 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: ENC1 },
+        Vector { _handler: ENC2 },
+        Vector { _handler: ENC3 },
+        Vector { _handler: ENC4 },
+        Vector { _handler: TMR1 },
+        Vector { _handler: TMR2 },
+        Vector { _handler: TMR3 },
+        Vector { _handler: TMR4 },
+        Vector { _handler: PWM2_0 },
+        Vector { _handler: PWM2_1 },
+        Vector { _handler: PWM2_2 },
+        Vector { _handler: PWM2_3 },
+        Vector {
+            _handler: PWM2_FAULT,
+        },
+        Vector { _handler: PWM3_0 },
+        Vector { _handler: PWM3_1 },
+        Vector { _handler: PWM3_2 },
+        Vector { _handler: PWM3_3 },
+        Vector {
+            _handler: PWM3_FAULT,
+        },
+        Vector { _handler: PWM4_0 },
+        Vector { _handler: PWM4_1 },
+        Vector { _handler: PWM4_2 },
+        Vector { _handler: PWM4_3 },
+        Vector {
+            _handler: PWM4_FAULT,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FLEXIO3 },
+        Vector {
+            _handler: GPIO6_7_8_9,
+        },
+    ];
+}
diff --git a/chips/imxrt1060/Cargo.toml b/chips/imxrt1060/Cargo.toml
new file mode 100644
index 0000000..aef1560
--- /dev/null
+++ b/chips/imxrt1060/Cargo.toml
@@ -0,0 +1,15 @@
+[package]
+name = "imxrt1060"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+cortex-m = { workspace = true }
+ral-registers = { workspace = true }
+
+imxrt-drivers-ccm-10xx = { workspace = true }
+imxrt-drivers-gpio = { workspace = true }
+imxrt-drivers-flexspi = { workspace = true }
+imxrt-drivers-iomuxc-10xx = { workspace = true }
+imxrt-drivers-lpspi = { workspace = true }
+imxrt-drivers-pit = { workspace = true }
diff --git a/chips/imxrt1060/build.rs b/chips/imxrt1060/build.rs
new file mode 100644
index 0000000..ac82cdd
--- /dev/null
+++ b/chips/imxrt1060/build.rs
@@ -0,0 +1,8 @@
+use std::{env, fs, path};
+
+fn main() {
+    let out_dir = path::PathBuf::from(env::var("OUT_DIR").unwrap());
+    fs::copy("device.x", out_dir.join("device.x")).unwrap();
+    fs::copy("device.x", out_dir.join("imxrt1060.x")).unwrap();
+    println!("cargo::rustc-link-search={}", out_dir.display());
+}
diff --git a/chips/imxrt1060/device.x b/chips/imxrt1060/device.x
new file mode 100644
index 0000000..3b1f962
--- /dev/null
+++ b/chips/imxrt1060/device.x
@@ -0,0 +1,146 @@
+PROVIDE(DMA0_DMA16 = DefaultHandler);
+PROVIDE(DMA1_DMA17 = DefaultHandler);
+PROVIDE(DMA2_DMA18 = DefaultHandler);
+PROVIDE(DMA3_DMA19 = DefaultHandler);
+PROVIDE(DMA4_DMA20 = DefaultHandler);
+PROVIDE(DMA5_DMA21 = DefaultHandler);
+PROVIDE(DMA6_DMA22 = DefaultHandler);
+PROVIDE(DMA7_DMA23 = DefaultHandler);
+PROVIDE(DMA8_DMA24 = DefaultHandler);
+PROVIDE(DMA9_DMA25 = DefaultHandler);
+PROVIDE(DMA10_DMA26 = DefaultHandler);
+PROVIDE(DMA11_DMA27 = DefaultHandler);
+PROVIDE(DMA12_DMA28 = DefaultHandler);
+PROVIDE(DMA13_DMA29 = DefaultHandler);
+PROVIDE(DMA14_DMA30 = DefaultHandler);
+PROVIDE(DMA15_DMA31 = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(LPUART1 = DefaultHandler);
+PROVIDE(LPUART2 = DefaultHandler);
+PROVIDE(LPUART3 = DefaultHandler);
+PROVIDE(LPUART4 = DefaultHandler);
+PROVIDE(LPUART5 = DefaultHandler);
+PROVIDE(LPUART6 = DefaultHandler);
+PROVIDE(LPUART7 = DefaultHandler);
+PROVIDE(LPUART8 = DefaultHandler);
+PROVIDE(LPI2C1 = DefaultHandler);
+PROVIDE(LPI2C2 = DefaultHandler);
+PROVIDE(LPI2C3 = DefaultHandler);
+PROVIDE(LPI2C4 = DefaultHandler);
+PROVIDE(LPSPI1 = DefaultHandler);
+PROVIDE(LPSPI2 = DefaultHandler);
+PROVIDE(LPSPI3 = DefaultHandler);
+PROVIDE(LPSPI4 = DefaultHandler);
+PROVIDE(CAN1 = DefaultHandler);
+PROVIDE(CAN2 = DefaultHandler);
+PROVIDE(FLEXRAM = DefaultHandler);
+PROVIDE(KPP = DefaultHandler);
+PROVIDE(TSC_DIG = DefaultHandler);
+PROVIDE(GPR_IRQ = DefaultHandler);
+PROVIDE(LCDIF = DefaultHandler);
+PROVIDE(CSI = DefaultHandler);
+PROVIDE(PXP = DefaultHandler);
+PROVIDE(WDOG2 = DefaultHandler);
+PROVIDE(SNVS_HP_WRAPPER = DefaultHandler);
+PROVIDE(SNVS_HP_WRAPPER_TZ = DefaultHandler);
+PROVIDE(SNVS_LP_WRAPPER = DefaultHandler);
+PROVIDE(CSU = DefaultHandler);
+PROVIDE(DCP = DefaultHandler);
+PROVIDE(DCP_VMI = DefaultHandler);
+PROVIDE(TRNG = DefaultHandler);
+PROVIDE(BEE = DefaultHandler);
+PROVIDE(SAI1 = DefaultHandler);
+PROVIDE(SAI2 = DefaultHandler);
+PROVIDE(SAI3_RX = DefaultHandler);
+PROVIDE(SAI3_TX = DefaultHandler);
+PROVIDE(SPDIF = DefaultHandler);
+PROVIDE(PMU_EVENT = DefaultHandler);
+PROVIDE(TEMP_LOW_HIGH = DefaultHandler);
+PROVIDE(TEMP_PANIC = DefaultHandler);
+PROVIDE(USB_PHY1 = DefaultHandler);
+PROVIDE(USB_PHY2 = DefaultHandler);
+PROVIDE(ADC1 = DefaultHandler);
+PROVIDE(ADC2 = DefaultHandler);
+PROVIDE(DCDC = DefaultHandler);
+PROVIDE(GPIO1_INT0 = DefaultHandler);
+PROVIDE(GPIO1_INT1 = DefaultHandler);
+PROVIDE(GPIO1_INT2 = DefaultHandler);
+PROVIDE(GPIO1_INT3 = DefaultHandler);
+PROVIDE(GPIO1_INT4 = DefaultHandler);
+PROVIDE(GPIO1_INT5 = DefaultHandler);
+PROVIDE(GPIO1_INT6 = DefaultHandler);
+PROVIDE(GPIO1_INT7 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO3_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO3_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO4_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO4_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_16_31 = DefaultHandler);
+PROVIDE(FLEXIO1 = DefaultHandler);
+PROVIDE(FLEXIO2 = DefaultHandler);
+PROVIDE(WDOG1 = DefaultHandler);
+PROVIDE(RTWDOG = DefaultHandler);
+PROVIDE(EWM = DefaultHandler);
+PROVIDE(CCM_1 = DefaultHandler);
+PROVIDE(CCM_2 = DefaultHandler);
+PROVIDE(GPC = DefaultHandler);
+PROVIDE(SRC = DefaultHandler);
+PROVIDE(GPT1 = DefaultHandler);
+PROVIDE(GPT2 = DefaultHandler);
+PROVIDE(PWM1_0 = DefaultHandler);
+PROVIDE(PWM1_1 = DefaultHandler);
+PROVIDE(PWM1_2 = DefaultHandler);
+PROVIDE(PWM1_3 = DefaultHandler);
+PROVIDE(PWM1_FAULT = DefaultHandler);
+PROVIDE(FLEXSPI2 = DefaultHandler);
+PROVIDE(FLEXSPI = DefaultHandler);
+PROVIDE(SEMC = DefaultHandler);
+PROVIDE(USDHC1 = DefaultHandler);
+PROVIDE(USDHC2 = DefaultHandler);
+PROVIDE(USB_OTG2 = DefaultHandler);
+PROVIDE(USB_OTG1 = DefaultHandler);
+PROVIDE(ENET = DefaultHandler);
+PROVIDE(ENET_1588_TIMER = DefaultHandler);
+PROVIDE(XBAR1_IRQ_0_1 = DefaultHandler);
+PROVIDE(XBAR1_IRQ_2_3 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ0 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ1 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ2 = DefaultHandler);
+PROVIDE(ADC_ETC_ERROR_IRQ = DefaultHandler);
+PROVIDE(PIT = DefaultHandler);
+PROVIDE(ACMP1 = DefaultHandler);
+PROVIDE(ACMP2 = DefaultHandler);
+PROVIDE(ACMP3 = DefaultHandler);
+PROVIDE(ACMP4 = DefaultHandler);
+PROVIDE(ENC1 = DefaultHandler);
+PROVIDE(ENC2 = DefaultHandler);
+PROVIDE(ENC3 = DefaultHandler);
+PROVIDE(ENC4 = DefaultHandler);
+PROVIDE(TMR1 = DefaultHandler);
+PROVIDE(TMR2 = DefaultHandler);
+PROVIDE(TMR3 = DefaultHandler);
+PROVIDE(TMR4 = DefaultHandler);
+PROVIDE(PWM2_0 = DefaultHandler);
+PROVIDE(PWM2_1 = DefaultHandler);
+PROVIDE(PWM2_2 = DefaultHandler);
+PROVIDE(PWM2_3 = DefaultHandler);
+PROVIDE(PWM2_FAULT = DefaultHandler);
+PROVIDE(PWM3_0 = DefaultHandler);
+PROVIDE(PWM3_1 = DefaultHandler);
+PROVIDE(PWM3_2 = DefaultHandler);
+PROVIDE(PWM3_3 = DefaultHandler);
+PROVIDE(PWM3_FAULT = DefaultHandler);
+PROVIDE(PWM4_0 = DefaultHandler);
+PROVIDE(PWM4_1 = DefaultHandler);
+PROVIDE(PWM4_2 = DefaultHandler);
+PROVIDE(PWM4_3 = DefaultHandler);
+PROVIDE(PWM4_FAULT = DefaultHandler);
+PROVIDE(ENET2 = DefaultHandler);
+PROVIDE(ENET2_1588_TIMER = DefaultHandler);
+PROVIDE(CAN3 = DefaultHandler);
+PROVIDE(FLEXIO3 = DefaultHandler);
+PROVIDE(GPIO6_7_8_9 = DefaultHandler);
diff --git a/chips/imxrt1060/src/iomuxc.rs b/chips/imxrt1060/src/iomuxc.rs
new file mode 100644
index 0000000..60272ea
--- /dev/null
+++ b/chips/imxrt1060/src/iomuxc.rs
@@ -0,0 +1,287 @@
+//! I/O multiplexing and configuration.
+
+pub type RegisterBlock = imxrt_drivers_iomuxc_10xx::iomuxc::RegisterBlock<20, 124, 231>;
+
+pub use imxrt_drivers_iomuxc_10xx::iomuxc::{SELECT_INPUT, SW_MUX_CTL_PAD, SW_PAD_CTL_PAD};
+
+/// Indices for `sw_[pad|mux]_ctl_pad` registers.
+pub mod pad {
+    pub const GPIO_EMC_00: usize = 0;
+    pub const GPIO_EMC_01: usize = 1;
+    pub const GPIO_EMC_02: usize = 2;
+    pub const GPIO_EMC_03: usize = 3;
+    pub const GPIO_EMC_04: usize = 4;
+    pub const GPIO_EMC_05: usize = 5;
+    pub const GPIO_EMC_06: usize = 6;
+    pub const GPIO_EMC_07: usize = 7;
+    pub const GPIO_EMC_08: usize = 8;
+    pub const GPIO_EMC_09: usize = 9;
+    pub const GPIO_EMC_10: usize = 10;
+    pub const GPIO_EMC_11: usize = 11;
+    pub const GPIO_EMC_12: usize = 12;
+    pub const GPIO_EMC_13: usize = 13;
+    pub const GPIO_EMC_14: usize = 14;
+    pub const GPIO_EMC_15: usize = 15;
+    pub const GPIO_EMC_16: usize = 16;
+    pub const GPIO_EMC_17: usize = 17;
+    pub const GPIO_EMC_18: usize = 18;
+    pub const GPIO_EMC_19: usize = 19;
+    pub const GPIO_EMC_20: usize = 20;
+    pub const GPIO_EMC_21: usize = 21;
+    pub const GPIO_EMC_22: usize = 22;
+    pub const GPIO_EMC_23: usize = 23;
+    pub const GPIO_EMC_24: usize = 24;
+    pub const GPIO_EMC_25: usize = 25;
+    pub const GPIO_EMC_26: usize = 26;
+    pub const GPIO_EMC_27: usize = 27;
+    pub const GPIO_EMC_28: usize = 28;
+    pub const GPIO_EMC_29: usize = 29;
+    pub const GPIO_EMC_30: usize = 30;
+    pub const GPIO_EMC_31: usize = 31;
+    pub const GPIO_EMC_32: usize = 32;
+    pub const GPIO_EMC_33: usize = 33;
+    pub const GPIO_EMC_34: usize = 34;
+    pub const GPIO_EMC_35: usize = 35;
+    pub const GPIO_EMC_36: usize = 36;
+    pub const GPIO_EMC_37: usize = 37;
+    pub const GPIO_EMC_38: usize = 38;
+    pub const GPIO_EMC_39: usize = 39;
+    pub const GPIO_EMC_40: usize = 40;
+    pub const GPIO_EMC_41: usize = 41;
+    pub const GPIO_AD_B0_04: usize = 46;
+    pub const GPIO_AD_B0_05: usize = 47;
+    pub const GPIO_AD_B0_06: usize = 48;
+    pub const GPIO_AD_B0_07: usize = 49;
+    pub const GPIO_AD_B0_08: usize = 50;
+    pub const GPIO_AD_B0_09: usize = 51;
+    pub const GPIO_AD_B0_10: usize = 52;
+    pub const GPIO_AD_B0_11: usize = 53;
+    pub const GPIO_AD_B0_12: usize = 54;
+    pub const GPIO_AD_B0_13: usize = 55;
+    pub const GPIO_AD_B0_14: usize = 56;
+    pub const GPIO_AD_B0_15: usize = 57;
+    pub const GPIO_AD_B1_00: usize = 58;
+    pub const GPIO_AD_B1_01: usize = 59;
+    pub const GPIO_AD_B1_02: usize = 60;
+    pub const GPIO_AD_B1_03: usize = 61;
+    pub const GPIO_AD_B1_04: usize = 62;
+    pub const GPIO_AD_B1_05: usize = 63;
+    pub const GPIO_AD_B1_06: usize = 64;
+    pub const GPIO_AD_B1_07: usize = 65;
+    pub const GPIO_B0_00: usize = 74;
+    pub const GPIO_B0_01: usize = 75;
+    pub const GPIO_B0_02: usize = 76;
+    pub const GPIO_B0_03: usize = 77;
+    pub const GPIO_B0_04: usize = 78;
+    pub const GPIO_B0_05: usize = 79;
+    pub const GPIO_B0_06: usize = 80;
+    pub const GPIO_B0_07: usize = 81;
+    pub const GPIO_B0_08: usize = 82;
+    pub const GPIO_B0_09: usize = 83;
+    pub const GPIO_B0_10: usize = 84;
+    pub const GPIO_B0_11: usize = 85;
+    pub const GPIO_B0_12: usize = 86;
+    pub const GPIO_B0_13: usize = 87;
+    pub const GPIO_B0_14: usize = 88;
+    pub const GPIO_B0_15: usize = 89;
+    pub const GPIO_B1_00: usize = 90;
+    pub const GPIO_B1_01: usize = 91;
+    pub const GPIO_B1_02: usize = 92;
+    pub const GPIO_B1_03: usize = 93;
+    pub const GPIO_B1_04: usize = 94;
+    pub const GPIO_B1_05: usize = 95;
+    pub const GPIO_B1_06: usize = 96;
+    pub const GPIO_B1_07: usize = 97;
+    pub const GPIO_B1_08: usize = 98;
+    pub const GPIO_B1_09: usize = 99;
+    pub const GPIO_B1_10: usize = 100;
+    pub const GPIO_B1_11: usize = 101;
+    pub const GPIO_B1_12: usize = 102;
+    pub const GPIO_B1_13: usize = 103;
+    pub const GPIO_B1_14: usize = 104;
+    pub const GPIO_B1_15: usize = 105;
+    pub const GPIO_SD_B0_00: usize = 106;
+    pub const GPIO_SD_B0_01: usize = 107;
+    pub const GPIO_SD_B0_02: usize = 108;
+    pub const GPIO_SD_B0_03: usize = 109;
+    pub const GPIO_SD_B0_04: usize = 110;
+    pub const GPIO_SD_B0_05: usize = 111;
+    pub const GPIO_SD_B1_00: usize = 112;
+    pub const GPIO_SD_B1_01: usize = 113;
+    pub const GPIO_SD_B1_02: usize = 114;
+    pub const GPIO_SD_B1_03: usize = 115;
+    pub const GPIO_SD_B1_04: usize = 116;
+    pub const GPIO_SD_B1_05: usize = 117;
+    pub const GPIO_SD_B1_06: usize = 118;
+    pub const GPIO_SD_B1_07: usize = 119;
+    pub const GPIO_SD_B1_08: usize = 120;
+    pub const GPIO_SD_B1_09: usize = 121;
+    pub const GPIO_SD_B1_10: usize = 122;
+    pub const GPIO_SD_B1_11: usize = 123;
+}
+
+/// Indices for `select_input` registers.
+pub mod select_input {
+    pub const ANATOP_USB_OTG1_ID: usize = 0;
+    pub const CCM_PMIC_READY: usize = 2;
+    pub const ENET_IPG_CLK_RMII: usize = 14;
+    pub const ENET_MDIO: usize = 15;
+    pub const ENET0_RXDATA: usize = 16;
+    pub const ENET1_RXDATA: usize = 17;
+    pub const ENET_RXEN: usize = 18;
+    pub const ENET_RXERR: usize = 19;
+    pub const ENET0_TIMER: usize = 20;
+    pub const ENET_TXCLK: usize = 21;
+    pub const FLEXCAN1_RX: usize = 22;
+    pub const FLEXCAN2_RX: usize = 23;
+    pub const FLEXPWM1_PWMA3: usize = 24;
+    pub const FLEXPWM1_PWMA0: usize = 25;
+    pub const FLEXPWM1_PWMA1: usize = 26;
+    pub const FLEXPWM1_PWMA2: usize = 27;
+    pub const FLEXPWM1_PWMB3: usize = 28;
+    pub const FLEXPWM1_PWMB0: usize = 29;
+    pub const FLEXPWM1_PWMB1: usize = 30;
+    pub const FLEXPWM1_PWMB2: usize = 31;
+    pub const FLEXPWM2_PWMA3: usize = 32;
+    pub const FLEXPWM2_PWMA0: usize = 33;
+    pub const FLEXPWM2_PWMA1: usize = 34;
+    pub const FLEXPWM2_PWMA2: usize = 35;
+    pub const FLEXPWM2_PWMB3: usize = 36;
+    pub const FLEXPWM2_PWMB0: usize = 37;
+    pub const FLEXPWM2_PWMB1: usize = 38;
+    pub const FLEXPWM2_PWMB2: usize = 39;
+    pub const FLEXPWM4_PWMA0: usize = 40;
+    pub const FLEXPWM4_PWMA1: usize = 41;
+    pub const FLEXPWM4_PWMA2: usize = 42;
+    pub const FLEXPWM4_PWMA3: usize = 43;
+    pub const FLEXSPIA_DQS: usize = 44;
+    pub const FLEXSPIA_DATA0: usize = 45;
+    pub const FLEXSPIA_DATA1: usize = 46;
+    pub const FLEXSPIA_DATA2: usize = 47;
+    pub const FLEXSPIA_DATA3: usize = 48;
+    pub const FLEXSPIB_DATA0: usize = 49;
+    pub const FLEXSPIB_DATA1: usize = 50;
+    pub const FLEXSPIB_DATA2: usize = 51;
+    pub const FLEXSPIB_DATA3: usize = 52;
+    pub const FLEXSPIA_SCK: usize = 53;
+    pub const LPI2C1_SCL: usize = 54;
+    pub const LPI2C1_SDA: usize = 55;
+    pub const LPI2C2_SCL: usize = 56;
+    pub const LPI2C2_SDA: usize = 57;
+    pub const LPI2C3_SCL: usize = 58;
+    pub const LPI2C3_SDA: usize = 59;
+    pub const LPI2C4_SCL: usize = 60;
+    pub const LPI2C4_SDA: usize = 61;
+    pub const LPSPI1_PCS0: usize = 62;
+    pub const LPSPI1_SCK: usize = 63;
+    pub const LPSPI1_SDI: usize = 64;
+    pub const LPSPI1_SDO: usize = 65;
+    pub const LPSPI2_PCS0: usize = 66;
+    pub const LPSPI2_SCK: usize = 67;
+    pub const LPSPI2_SDI: usize = 68;
+    pub const LPSPI2_SDO: usize = 69;
+    pub const LPSPI3_PCS0: usize = 74;
+    pub const LPSPI3_SCK: usize = 75;
+    pub const LPSPI3_SDI: usize = 76;
+    pub const LPSPI3_SDO: usize = 77;
+    pub const LPUART2_RX: usize = 78;
+    pub const LPUART2_TX: usize = 79;
+    pub const LPUART3_CTS_B: usize = 80;
+    pub const LPUART3_RX: usize = 81;
+    pub const LPUART3_TX: usize = 82;
+    pub const LPUART4_RX: usize = 83;
+    pub const LPUART4_TX: usize = 84;
+    pub const LPUART5_RX: usize = 85;
+    pub const LPUART5_TX: usize = 86;
+    pub const LPUART6_RX: usize = 87;
+    pub const LPUART6_TX: usize = 88;
+    pub const LPUART7_RX: usize = 89;
+    pub const LPUART7_TX: usize = 90;
+    pub const LPUART8_RX: usize = 91;
+    pub const LPUART8_TX: usize = 92;
+    pub const NMI: usize = 93;
+    pub const QTIMER2_TIMER0: usize = 94;
+    pub const QTIMER2_TIMER1: usize = 95;
+    pub const QTIMER2_TIMER2: usize = 96;
+    pub const QTIMER2_TIMER3: usize = 97;
+    pub const QTIMER3_TIMER0: usize = 98;
+    pub const QTIMER3_TIMER1: usize = 99;
+    pub const QTIMER3_TIMER2: usize = 100;
+    pub const QTIMER3_TIMER3: usize = 101;
+    pub const SAI1_MCLK2: usize = 102;
+    pub const SAI1_RX_BCLK: usize = 103;
+    pub const SAI1_RX_DATA0: usize = 104;
+    pub const SAI1_RX_DATA1: usize = 105;
+    pub const SAI1_RX_DATA2: usize = 106;
+    pub const SAI1_RX_DATA3: usize = 107;
+    pub const SAI1_RX_SYNC: usize = 108;
+    pub const SAI1_TX_BCLK: usize = 109;
+    pub const SAI1_TX_SYNC: usize = 110;
+    pub const SAI2_MCLK2: usize = 111;
+    pub const SAI2_RX_BCLK: usize = 112;
+    pub const SAI2_RX_DATA0: usize = 113;
+    pub const SAI2_RX_SYNC: usize = 114;
+    pub const SAI2_TX_BCLK: usize = 115;
+    pub const SAI2_TX_SYNC: usize = 116;
+    pub const SPDIF_IN: usize = 117;
+    pub const USB_OTG1_OC: usize = 119;
+    pub const USDHC1_CD_B: usize = 120;
+    pub const USDHC1_WP: usize = 121;
+    pub const USDHC2_CLK: usize = 122;
+    pub const USDHC2_CD_B: usize = 123;
+    pub const USDHC2_CMD: usize = 124;
+    pub const USDHC2_DATA0: usize = 125;
+    pub const USDHC2_DATA1: usize = 126;
+    pub const USDHC2_DATA2: usize = 127;
+    pub const USDHC2_DATA3: usize = 128;
+    pub const USDHC2_DATA4: usize = 129;
+    pub const USDHC2_DATA5: usize = 130;
+    pub const USDHC2_DATA6: usize = 131;
+    pub const USDHC2_DATA7: usize = 132;
+    pub const USDHC2_WP: usize = 133;
+    pub const XBAR1_IN02: usize = 134;
+    pub const XBAR1_IN03: usize = 135;
+    pub const XBAR1_IN04: usize = 136;
+    pub const XBAR1_IN05: usize = 137;
+    pub const XBAR1_IN06: usize = 138;
+    pub const XBAR1_IN07: usize = 139;
+    pub const XBAR1_IN08: usize = 140;
+    pub const XBAR1_IN09: usize = 141;
+    pub const XBAR1_IN17: usize = 142;
+    pub const XBAR1_IN18: usize = 143;
+    pub const XBAR1_IN20: usize = 144;
+    pub const XBAR1_IN22: usize = 145;
+    pub const XBAR1_IN23: usize = 146;
+    pub const XBAR1_IN24: usize = 147;
+    pub const XBAR1_IN14: usize = 148;
+    pub const XBAR1_IN15: usize = 149;
+    pub const XBAR1_IN16: usize = 150;
+    pub const XBAR1_IN25: usize = 151;
+    pub const XBAR1_IN19: usize = 152;
+    pub const XBAR1_IN21: usize = 153;
+    pub const FLEXSPI2_IPP_IND_DQS_FA: usize = 206;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT0: usize = 207;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT1: usize = 208;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT2: usize = 209;
+    pub const FLEXSPI2_IPP_IND_IO_FA_BIT3: usize = 210;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT0: usize = 211;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT1: usize = 212;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT2: usize = 213;
+    pub const FLEXSPI2_IPP_IND_IO_FB_BIT3: usize = 214;
+    pub const FLEXSPI2_IPP_IND_SCK_FA: usize = 215;
+    pub const FLEXSPI2_IPP_IND_SCK_FB: usize = 216;
+    pub const GPT1_IPP_IND_CAPIN1: usize = 217;
+    pub const GPT1_IPP_IND_CAPIN2: usize = 218;
+    pub const GPT1_IPP_IND_CLKIN: usize = 219;
+    pub const GPT2_IPP_IND_CAPIN1: usize = 220;
+    pub const GPT2_IPP_IND_CAPIN2: usize = 221;
+    pub const GPT2_IPP_IND_CLKIN: usize = 222;
+    pub const SAI3_IPG_CLK_SAI_MCLK_S: usize = 223;
+    pub const SAI3_IPP_IND_SAI_RXBCLK: usize = 224;
+    pub const SAI3_IPP_IND_SAI_RXDATA_S: usize = 225;
+    pub const SAI3_IPP_IND_SAI_RXSYNC: usize = 226;
+    pub const SAI3_IPP_IND_SAI_TXBCLK: usize = 227;
+    pub const SAI3_IPP_IND_SAI_TXSYNC: usize = 228;
+    pub const SEMC_I_IPP_IND_DQS4: usize = 229;
+    pub const CANFD_IPP_IND_CANRX: usize = 230;
+}
diff --git a/chips/imxrt1060/src/lib.rs b/chips/imxrt1060/src/lib.rs
new file mode 100644
index 0000000..0ac779b
--- /dev/null
+++ b/chips/imxrt1060/src/lib.rs
@@ -0,0 +1,54 @@
+#![no_std]
+
+pub use ral_registers::{Instance, modify_reg, read_reg, write_reg};
+
+mod rt;
+pub use rt::*;
+
+pub mod iomuxc;
+
+/// Clock control module.
+pub mod ccm {
+    pub use imxrt_drivers_ccm_10xx::ahb::pll1::*;
+
+    pub use imxrt_drivers_ccm_10xx::ccm::{
+        LowPowerMode, ahb_clk, clock_gate, flexspi1_clk_axi_semc as flexspi1_clk, ipg_clk,
+        low_power_mode, lpi2c_clk, lpspi_clk, perclk_clk, set_low_power_mode, uart_clk,
+    };
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::{pll2, pll3};
+
+    pub use imxrt_drivers_ccm_10xx::ccm::{
+        arm_divider, periph_clk2, pre_periph_clk_pll1 as pre_periph_clk,
+    };
+
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::pll7;
+    pub use imxrt_drivers_ccm_10xx::ccm_analog::{pll1, pll6};
+}
+
+pub use imxrt_drivers_flexspi as flexspi;
+pub use imxrt_drivers_lpspi as lpspi;
+pub use imxrt_drivers_pit as pit;
+
+/// Peripheral instances.
+pub mod instances {
+    ral_registers::instances! {
+        // Safety: The reference manual confirms there are register
+        // blocks at this address matching this shape.
+        unsafe {
+            /// Access CCM registers.
+            pub ccm<imxrt_drivers_ccm_10xx::ral::ccm::RegisterBlock> = 0x400F_C000;
+            /// Access CCM\_ANALOG registers.
+            pub ccm_analog<imxrt_drivers_ccm_10xx::ral::ccm_analog::RegisterBlock> = 0x400D_8000;
+
+            pub flexspi1<crate::flexspi::RegisterBlock> = 0x402A_8000;
+            pub flexspi2<crate::flexspi::RegisterBlock> = 0x402A_4000;
+
+            pub pit<crate::pit::RegisterBlock> = 0x4008_4000;
+
+            pub lpspi1<crate::lpspi::RegisterBlock> = 0x4039_4000;
+            pub lpspi2<crate::lpspi::RegisterBlock> = 0x4039_8000;
+            pub lpspi3<crate::lpspi::RegisterBlock> = 0x4039_C000;
+            pub lpspi4<crate::lpspi::RegisterBlock> = 0x403A_0000;
+        }
+    }
+}
diff --git a/chips/imxrt1060/src/rt.rs b/chips/imxrt1060/src/rt.rs
new file mode 100644
index 0000000..a54aa2f
--- /dev/null
+++ b/chips/imxrt1060/src/rt.rs
@@ -0,0 +1,729 @@
+#![allow(non_camel_case_types)]
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - DMA0_DMA16"]
+    DMA0_DMA16 = 0,
+    #[doc = "1 - DMA1_DMA17"]
+    DMA1_DMA17 = 1,
+    #[doc = "2 - DMA2_DMA18"]
+    DMA2_DMA18 = 2,
+    #[doc = "3 - DMA3_DMA19"]
+    DMA3_DMA19 = 3,
+    #[doc = "4 - DMA4_DMA20"]
+    DMA4_DMA20 = 4,
+    #[doc = "5 - DMA5_DMA21"]
+    DMA5_DMA21 = 5,
+    #[doc = "6 - DMA6_DMA22"]
+    DMA6_DMA22 = 6,
+    #[doc = "7 - DMA7_DMA23"]
+    DMA7_DMA23 = 7,
+    #[doc = "8 - DMA8_DMA24"]
+    DMA8_DMA24 = 8,
+    #[doc = "9 - DMA9_DMA25"]
+    DMA9_DMA25 = 9,
+    #[doc = "10 - DMA10_DMA26"]
+    DMA10_DMA26 = 10,
+    #[doc = "11 - DMA11_DMA27"]
+    DMA11_DMA27 = 11,
+    #[doc = "12 - DMA12_DMA28"]
+    DMA12_DMA28 = 12,
+    #[doc = "13 - DMA13_DMA29"]
+    DMA13_DMA29 = 13,
+    #[doc = "14 - DMA14_DMA30"]
+    DMA14_DMA30 = 14,
+    #[doc = "15 - DMA15_DMA31"]
+    DMA15_DMA31 = 15,
+    #[doc = "16 - DMA_ERROR"]
+    DMA_ERROR = 16,
+    #[doc = "20 - LPUART1"]
+    LPUART1 = 20,
+    #[doc = "21 - LPUART2"]
+    LPUART2 = 21,
+    #[doc = "22 - LPUART3"]
+    LPUART3 = 22,
+    #[doc = "23 - LPUART4"]
+    LPUART4 = 23,
+    #[doc = "24 - LPUART5"]
+    LPUART5 = 24,
+    #[doc = "25 - LPUART6"]
+    LPUART6 = 25,
+    #[doc = "26 - LPUART7"]
+    LPUART7 = 26,
+    #[doc = "27 - LPUART8"]
+    LPUART8 = 27,
+    #[doc = "28 - LPI2C1"]
+    LPI2C1 = 28,
+    #[doc = "29 - LPI2C2"]
+    LPI2C2 = 29,
+    #[doc = "30 - LPI2C3"]
+    LPI2C3 = 30,
+    #[doc = "31 - LPI2C4"]
+    LPI2C4 = 31,
+    #[doc = "32 - LPSPI1"]
+    LPSPI1 = 32,
+    #[doc = "33 - LPSPI2"]
+    LPSPI2 = 33,
+    #[doc = "34 - LPSPI3"]
+    LPSPI3 = 34,
+    #[doc = "35 - LPSPI4"]
+    LPSPI4 = 35,
+    #[doc = "36 - CAN1"]
+    CAN1 = 36,
+    #[doc = "37 - CAN2"]
+    CAN2 = 37,
+    #[doc = "38 - FLEXRAM"]
+    FLEXRAM = 38,
+    #[doc = "39 - KPP"]
+    KPP = 39,
+    #[doc = "40 - TSC_DIG"]
+    TSC_DIG = 40,
+    #[doc = "41 - GPR (aka \"GPC\") interrupt request"]
+    GPR_IRQ = 41,
+    #[doc = "42 - LCDIF"]
+    LCDIF = 42,
+    #[doc = "43 - CSI"]
+    CSI = 43,
+    #[doc = "44 - PXP"]
+    PXP = 44,
+    #[doc = "45 - WDOG2"]
+    WDOG2 = 45,
+    #[doc = "46 - SNVS_HP_WRAPPER"]
+    SNVS_HP_WRAPPER = 46,
+    #[doc = "47 - SNVS_HP_WRAPPER_TZ"]
+    SNVS_HP_WRAPPER_TZ = 47,
+    #[doc = "48 - SNVS_LP_WRAPPER"]
+    SNVS_LP_WRAPPER = 48,
+    #[doc = "49 - CSU"]
+    CSU = 49,
+    #[doc = "50 - DCP"]
+    DCP = 50,
+    #[doc = "51 - DCP_VMI"]
+    DCP_VMI = 51,
+    #[doc = "53 - TRNG"]
+    TRNG = 53,
+    #[doc = "55 - BEE"]
+    BEE = 55,
+    #[doc = "56 - SAI1"]
+    SAI1 = 56,
+    #[doc = "57 - SAI2"]
+    SAI2 = 57,
+    #[doc = "58 - SAI3_RX"]
+    SAI3_RX = 58,
+    #[doc = "59 - SAI3_TX"]
+    SAI3_TX = 59,
+    #[doc = "60 - SPDIF"]
+    SPDIF = 60,
+    #[doc = "61 - PMU_EVENT"]
+    PMU_EVENT = 61,
+    #[doc = "63 - TEMP_LOW_HIGH"]
+    TEMP_LOW_HIGH = 63,
+    #[doc = "64 - TEMP_PANIC"]
+    TEMP_PANIC = 64,
+    #[doc = "65 - USB_PHY1"]
+    USB_PHY1 = 65,
+    #[doc = "66 - USB_PHY2"]
+    USB_PHY2 = 66,
+    #[doc = "67 - ADC1"]
+    ADC1 = 67,
+    #[doc = "68 - ADC2"]
+    ADC2 = 68,
+    #[doc = "69 - DCDC"]
+    DCDC = 69,
+    #[doc = "72 - GPIO1_INT0"]
+    GPIO1_INT0 = 72,
+    #[doc = "73 - GPIO1_INT1"]
+    GPIO1_INT1 = 73,
+    #[doc = "74 - GPIO1_INT2"]
+    GPIO1_INT2 = 74,
+    #[doc = "75 - GPIO1_INT3"]
+    GPIO1_INT3 = 75,
+    #[doc = "76 - GPIO1_INT4"]
+    GPIO1_INT4 = 76,
+    #[doc = "77 - GPIO1_INT5"]
+    GPIO1_INT5 = 77,
+    #[doc = "78 - GPIO1_INT6"]
+    GPIO1_INT6 = 78,
+    #[doc = "79 - GPIO1_INT7"]
+    GPIO1_INT7 = 79,
+    #[doc = "80 - GPIO1_COMBINED_0_15"]
+    GPIO1_COMBINED_0_15 = 80,
+    #[doc = "81 - GPIO1_COMBINED_16_31"]
+    GPIO1_COMBINED_16_31 = 81,
+    #[doc = "82 - GPIO2_COMBINED_0_15"]
+    GPIO2_COMBINED_0_15 = 82,
+    #[doc = "83 - GPIO2_COMBINED_16_31"]
+    GPIO2_COMBINED_16_31 = 83,
+    #[doc = "84 - GPIO3_COMBINED_0_15"]
+    GPIO3_COMBINED_0_15 = 84,
+    #[doc = "85 - GPIO3_COMBINED_16_31"]
+    GPIO3_COMBINED_16_31 = 85,
+    #[doc = "86 - GPIO4_COMBINED_0_15"]
+    GPIO4_COMBINED_0_15 = 86,
+    #[doc = "87 - GPIO4_COMBINED_16_31"]
+    GPIO4_COMBINED_16_31 = 87,
+    #[doc = "88 - GPIO5_COMBINED_0_15"]
+    GPIO5_COMBINED_0_15 = 88,
+    #[doc = "89 - GPIO5_COMBINED_16_31"]
+    GPIO5_COMBINED_16_31 = 89,
+    #[doc = "90 - FLEXIO1"]
+    FLEXIO1 = 90,
+    #[doc = "91 - FLEXIO2"]
+    FLEXIO2 = 91,
+    #[doc = "92 - WDOG1"]
+    WDOG1 = 92,
+    #[doc = "93 - RTWDOG"]
+    RTWDOG = 93,
+    #[doc = "94 - EWM"]
+    EWM = 94,
+    #[doc = "95 - CCM_1"]
+    CCM_1 = 95,
+    #[doc = "96 - CCM_2"]
+    CCM_2 = 96,
+    #[doc = "97 - GPC"]
+    GPC = 97,
+    #[doc = "98 - SRC"]
+    SRC = 98,
+    #[doc = "100 - GPT1"]
+    GPT1 = 100,
+    #[doc = "101 - GPT2"]
+    GPT2 = 101,
+    #[doc = "102 - PWM1_0"]
+    PWM1_0 = 102,
+    #[doc = "103 - PWM1_1"]
+    PWM1_1 = 103,
+    #[doc = "104 - PWM1_2"]
+    PWM1_2 = 104,
+    #[doc = "105 - PWM1_3"]
+    PWM1_3 = 105,
+    #[doc = "106 - PWM1_FAULT"]
+    PWM1_FAULT = 106,
+    #[doc = "107 - FLEXSPI2"]
+    FLEXSPI2 = 107,
+    #[doc = "108 - FLEXSPI"]
+    FLEXSPI = 108,
+    #[doc = "109 - SEMC"]
+    SEMC = 109,
+    #[doc = "110 - USDHC1"]
+    USDHC1 = 110,
+    #[doc = "111 - USDHC2"]
+    USDHC2 = 111,
+    #[doc = "112 - USB_OTG2"]
+    USB_OTG2 = 112,
+    #[doc = "113 - USB_OTG1"]
+    USB_OTG1 = 113,
+    #[doc = "114 - ENET"]
+    ENET = 114,
+    #[doc = "115 - ENET_1588_TIMER"]
+    ENET_1588_TIMER = 115,
+    #[doc = "116 - XBAR1_IRQ_0_1"]
+    XBAR1_IRQ_0_1 = 116,
+    #[doc = "117 - XBAR1_IRQ_2_3"]
+    XBAR1_IRQ_2_3 = 117,
+    #[doc = "118 - ADC_ETC_IRQ0"]
+    ADC_ETC_IRQ0 = 118,
+    #[doc = "119 - ADC_ETC_IRQ1"]
+    ADC_ETC_IRQ1 = 119,
+    #[doc = "120 - ADC_ETC_IRQ2"]
+    ADC_ETC_IRQ2 = 120,
+    #[doc = "121 - ADC_ETC_ERROR_IRQ"]
+    ADC_ETC_ERROR_IRQ = 121,
+    #[doc = "122 - PIT"]
+    PIT = 122,
+    #[doc = "123 - ACMP1"]
+    ACMP1 = 123,
+    #[doc = "124 - ACMP2"]
+    ACMP2 = 124,
+    #[doc = "125 - ACMP3"]
+    ACMP3 = 125,
+    #[doc = "126 - ACMP4"]
+    ACMP4 = 126,
+    #[doc = "129 - ENC1"]
+    ENC1 = 129,
+    #[doc = "130 - ENC2"]
+    ENC2 = 130,
+    #[doc = "131 - ENC3"]
+    ENC3 = 131,
+    #[doc = "132 - ENC4"]
+    ENC4 = 132,
+    #[doc = "133 - TMR1"]
+    TMR1 = 133,
+    #[doc = "134 - TMR2"]
+    TMR2 = 134,
+    #[doc = "135 - TMR3"]
+    TMR3 = 135,
+    #[doc = "136 - TMR4"]
+    TMR4 = 136,
+    #[doc = "137 - PWM2_0"]
+    PWM2_0 = 137,
+    #[doc = "138 - PWM2_1"]
+    PWM2_1 = 138,
+    #[doc = "139 - PWM2_2"]
+    PWM2_2 = 139,
+    #[doc = "140 - PWM2_3"]
+    PWM2_3 = 140,
+    #[doc = "141 - PWM2_FAULT"]
+    PWM2_FAULT = 141,
+    #[doc = "142 - PWM3_0"]
+    PWM3_0 = 142,
+    #[doc = "143 - PWM3_1"]
+    PWM3_1 = 143,
+    #[doc = "144 - PWM3_2"]
+    PWM3_2 = 144,
+    #[doc = "145 - PWM3_3"]
+    PWM3_3 = 145,
+    #[doc = "146 - PWM3_FAULT"]
+    PWM3_FAULT = 146,
+    #[doc = "147 - PWM4_0"]
+    PWM4_0 = 147,
+    #[doc = "148 - PWM4_1"]
+    PWM4_1 = 148,
+    #[doc = "149 - PWM4_2"]
+    PWM4_2 = 149,
+    #[doc = "150 - PWM4_3"]
+    PWM4_3 = 150,
+    #[doc = "151 - PWM4_FAULT"]
+    PWM4_FAULT = 151,
+    #[doc = "152 - ENET2"]
+    ENET2 = 152,
+    #[doc = "153 - ENET2_1588_TIMER"]
+    ENET2_1588_TIMER = 153,
+    #[doc = "154 - CAN3"]
+    CAN3 = 154,
+    #[doc = "156 - FLEXIO3"]
+    FLEXIO3 = 156,
+    #[doc = "157 - GPIO6_7_8_9"]
+    GPIO6_7_8_9 = 157,
+}
+pub type interrupt = Interrupt;
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+
+mod _vectors {
+    unsafe extern "C" {
+        fn DMA0_DMA16();
+        fn DMA1_DMA17();
+        fn DMA2_DMA18();
+        fn DMA3_DMA19();
+        fn DMA4_DMA20();
+        fn DMA5_DMA21();
+        fn DMA6_DMA22();
+        fn DMA7_DMA23();
+        fn DMA8_DMA24();
+        fn DMA9_DMA25();
+        fn DMA10_DMA26();
+        fn DMA11_DMA27();
+        fn DMA12_DMA28();
+        fn DMA13_DMA29();
+        fn DMA14_DMA30();
+        fn DMA15_DMA31();
+        fn DMA_ERROR();
+        fn LPUART1();
+        fn LPUART2();
+        fn LPUART3();
+        fn LPUART4();
+        fn LPUART5();
+        fn LPUART6();
+        fn LPUART7();
+        fn LPUART8();
+        fn LPI2C1();
+        fn LPI2C2();
+        fn LPI2C3();
+        fn LPI2C4();
+        fn LPSPI1();
+        fn LPSPI2();
+        fn LPSPI3();
+        fn LPSPI4();
+        fn CAN1();
+        fn CAN2();
+        fn FLEXRAM();
+        fn KPP();
+        fn TSC_DIG();
+        fn GPR_IRQ();
+        fn LCDIF();
+        fn CSI();
+        fn PXP();
+        fn WDOG2();
+        fn SNVS_HP_WRAPPER();
+        fn SNVS_HP_WRAPPER_TZ();
+        fn SNVS_LP_WRAPPER();
+        fn CSU();
+        fn DCP();
+        fn DCP_VMI();
+        fn TRNG();
+        fn BEE();
+        fn SAI1();
+        fn SAI2();
+        fn SAI3_RX();
+        fn SAI3_TX();
+        fn SPDIF();
+        fn PMU_EVENT();
+        fn TEMP_LOW_HIGH();
+        fn TEMP_PANIC();
+        fn USB_PHY1();
+        fn USB_PHY2();
+        fn ADC1();
+        fn ADC2();
+        fn DCDC();
+        fn GPIO1_INT0();
+        fn GPIO1_INT1();
+        fn GPIO1_INT2();
+        fn GPIO1_INT3();
+        fn GPIO1_INT4();
+        fn GPIO1_INT5();
+        fn GPIO1_INT6();
+        fn GPIO1_INT7();
+        fn GPIO1_COMBINED_0_15();
+        fn GPIO1_COMBINED_16_31();
+        fn GPIO2_COMBINED_0_15();
+        fn GPIO2_COMBINED_16_31();
+        fn GPIO3_COMBINED_0_15();
+        fn GPIO3_COMBINED_16_31();
+        fn GPIO4_COMBINED_0_15();
+        fn GPIO4_COMBINED_16_31();
+        fn GPIO5_COMBINED_0_15();
+        fn GPIO5_COMBINED_16_31();
+        fn FLEXIO1();
+        fn FLEXIO2();
+        fn WDOG1();
+        fn RTWDOG();
+        fn EWM();
+        fn CCM_1();
+        fn CCM_2();
+        fn GPC();
+        fn SRC();
+        fn GPT1();
+        fn GPT2();
+        fn PWM1_0();
+        fn PWM1_1();
+        fn PWM1_2();
+        fn PWM1_3();
+        fn PWM1_FAULT();
+        fn FLEXSPI2();
+        fn FLEXSPI();
+        fn SEMC();
+        fn USDHC1();
+        fn USDHC2();
+        fn USB_OTG2();
+        fn USB_OTG1();
+        fn ENET();
+        fn ENET_1588_TIMER();
+        fn XBAR1_IRQ_0_1();
+        fn XBAR1_IRQ_2_3();
+        fn ADC_ETC_IRQ0();
+        fn ADC_ETC_IRQ1();
+        fn ADC_ETC_IRQ2();
+        fn ADC_ETC_ERROR_IRQ();
+        fn PIT();
+        fn ACMP1();
+        fn ACMP2();
+        fn ACMP3();
+        fn ACMP4();
+        fn ENC1();
+        fn ENC2();
+        fn ENC3();
+        fn ENC4();
+        fn TMR1();
+        fn TMR2();
+        fn TMR3();
+        fn TMR4();
+        fn PWM2_0();
+        fn PWM2_1();
+        fn PWM2_2();
+        fn PWM2_3();
+        fn PWM2_FAULT();
+        fn PWM3_0();
+        fn PWM3_1();
+        fn PWM3_2();
+        fn PWM3_3();
+        fn PWM3_FAULT();
+        fn PWM4_0();
+        fn PWM4_1();
+        fn PWM4_2();
+        fn PWM4_3();
+        fn PWM4_FAULT();
+        fn ENET2();
+        fn ENET2_1588_TIMER();
+        fn CAN3();
+        fn FLEXIO3();
+        fn GPIO6_7_8_9();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".vector_table.interrupts"))]
+    #[unsafe(no_mangle)]
+    pub static __INTERRUPTS: [Vector; 158] = [
+        Vector {
+            _handler: DMA0_DMA16,
+        },
+        Vector {
+            _handler: DMA1_DMA17,
+        },
+        Vector {
+            _handler: DMA2_DMA18,
+        },
+        Vector {
+            _handler: DMA3_DMA19,
+        },
+        Vector {
+            _handler: DMA4_DMA20,
+        },
+        Vector {
+            _handler: DMA5_DMA21,
+        },
+        Vector {
+            _handler: DMA6_DMA22,
+        },
+        Vector {
+            _handler: DMA7_DMA23,
+        },
+        Vector {
+            _handler: DMA8_DMA24,
+        },
+        Vector {
+            _handler: DMA9_DMA25,
+        },
+        Vector {
+            _handler: DMA10_DMA26,
+        },
+        Vector {
+            _handler: DMA11_DMA27,
+        },
+        Vector {
+            _handler: DMA12_DMA28,
+        },
+        Vector {
+            _handler: DMA13_DMA29,
+        },
+        Vector {
+            _handler: DMA14_DMA30,
+        },
+        Vector {
+            _handler: DMA15_DMA31,
+        },
+        Vector {
+            _handler: DMA_ERROR,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: LPUART2 },
+        Vector { _handler: LPUART3 },
+        Vector { _handler: LPUART4 },
+        Vector { _handler: LPUART5 },
+        Vector { _handler: LPUART6 },
+        Vector { _handler: LPUART7 },
+        Vector { _handler: LPUART8 },
+        Vector { _handler: LPI2C1 },
+        Vector { _handler: LPI2C2 },
+        Vector { _handler: LPI2C3 },
+        Vector { _handler: LPI2C4 },
+        Vector { _handler: LPSPI1 },
+        Vector { _handler: LPSPI2 },
+        Vector { _handler: LPSPI3 },
+        Vector { _handler: LPSPI4 },
+        Vector { _handler: CAN1 },
+        Vector { _handler: CAN2 },
+        Vector { _handler: FLEXRAM },
+        Vector { _handler: KPP },
+        Vector { _handler: TSC_DIG },
+        Vector { _handler: GPR_IRQ },
+        Vector { _handler: LCDIF },
+        Vector { _handler: CSI },
+        Vector { _handler: PXP },
+        Vector { _handler: WDOG2 },
+        Vector {
+            _handler: SNVS_HP_WRAPPER,
+        },
+        Vector {
+            _handler: SNVS_HP_WRAPPER_TZ,
+        },
+        Vector {
+            _handler: SNVS_LP_WRAPPER,
+        },
+        Vector { _handler: CSU },
+        Vector { _handler: DCP },
+        Vector { _handler: DCP_VMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: TRNG },
+        Vector { _reserved: 0 },
+        Vector { _handler: BEE },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SAI3_RX },
+        Vector { _handler: SAI3_TX },
+        Vector { _handler: SPDIF },
+        Vector {
+            _handler: PMU_EVENT,
+        },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: TEMP_LOW_HIGH,
+        },
+        Vector {
+            _handler: TEMP_PANIC,
+        },
+        Vector { _handler: USB_PHY1 },
+        Vector { _handler: USB_PHY2 },
+        Vector { _handler: ADC1 },
+        Vector { _handler: ADC2 },
+        Vector { _handler: DCDC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: GPIO1_INT0,
+        },
+        Vector {
+            _handler: GPIO1_INT1,
+        },
+        Vector {
+            _handler: GPIO1_INT2,
+        },
+        Vector {
+            _handler: GPIO1_INT3,
+        },
+        Vector {
+            _handler: GPIO1_INT4,
+        },
+        Vector {
+            _handler: GPIO1_INT5,
+        },
+        Vector {
+            _handler: GPIO1_INT6,
+        },
+        Vector {
+            _handler: GPIO1_INT7,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_16_31,
+        },
+        Vector { _handler: FLEXIO1 },
+        Vector { _handler: FLEXIO2 },
+        Vector { _handler: WDOG1 },
+        Vector { _handler: RTWDOG },
+        Vector { _handler: EWM },
+        Vector { _handler: CCM_1 },
+        Vector { _handler: CCM_2 },
+        Vector { _handler: GPC },
+        Vector { _handler: SRC },
+        Vector { _reserved: 0 },
+        Vector { _handler: GPT1 },
+        Vector { _handler: GPT2 },
+        Vector { _handler: PWM1_0 },
+        Vector { _handler: PWM1_1 },
+        Vector { _handler: PWM1_2 },
+        Vector { _handler: PWM1_3 },
+        Vector {
+            _handler: PWM1_FAULT,
+        },
+        Vector { _handler: FLEXSPI2 },
+        Vector { _handler: FLEXSPI },
+        Vector { _handler: SEMC },
+        Vector { _handler: USDHC1 },
+        Vector { _handler: USDHC2 },
+        Vector { _handler: USB_OTG2 },
+        Vector { _handler: USB_OTG1 },
+        Vector { _handler: ENET },
+        Vector {
+            _handler: ENET_1588_TIMER,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_0_1,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_2_3,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ0,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ1,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ2,
+        },
+        Vector {
+            _handler: ADC_ETC_ERROR_IRQ,
+        },
+        Vector { _handler: PIT },
+        Vector { _handler: ACMP1 },
+        Vector { _handler: ACMP2 },
+        Vector { _handler: ACMP3 },
+        Vector { _handler: ACMP4 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: ENC1 },
+        Vector { _handler: ENC2 },
+        Vector { _handler: ENC3 },
+        Vector { _handler: ENC4 },
+        Vector { _handler: TMR1 },
+        Vector { _handler: TMR2 },
+        Vector { _handler: TMR3 },
+        Vector { _handler: TMR4 },
+        Vector { _handler: PWM2_0 },
+        Vector { _handler: PWM2_1 },
+        Vector { _handler: PWM2_2 },
+        Vector { _handler: PWM2_3 },
+        Vector {
+            _handler: PWM2_FAULT,
+        },
+        Vector { _handler: PWM3_0 },
+        Vector { _handler: PWM3_1 },
+        Vector { _handler: PWM3_2 },
+        Vector { _handler: PWM3_3 },
+        Vector {
+            _handler: PWM3_FAULT,
+        },
+        Vector { _handler: PWM4_0 },
+        Vector { _handler: PWM4_1 },
+        Vector { _handler: PWM4_2 },
+        Vector { _handler: PWM4_3 },
+        Vector {
+            _handler: PWM4_FAULT,
+        },
+        Vector { _handler: ENET2 },
+        Vector {
+            _handler: ENET2_1588_TIMER,
+        },
+        Vector { _handler: CAN3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FLEXIO3 },
+        Vector {
+            _handler: GPIO6_7_8_9,
+        },
+    ];
+}
diff --git a/chips/imxrt1160/Cargo.toml b/chips/imxrt1160/Cargo.toml
new file mode 100644
index 0000000..6cc826a
--- /dev/null
+++ b/chips/imxrt1160/Cargo.toml
@@ -0,0 +1,20 @@
+[package]
+name = "imxrt1160"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+cortex-m = { workspace = true }
+ral-registers = { workspace = true }
+
+imxrt-drivers-ccm-11xx = { workspace = true }
+imxrt-drivers-edma = { workspace = true }
+imxrt-drivers-enet = { workspace = true }
+imxrt-drivers-flexspi = { workspace = true }
+imxrt-drivers-gpio = { workspace = true }
+imxrt-drivers-gpc-11xx = { workspace = true }
+imxrt-drivers-iomuxc-11xx = { workspace = true }
+imxrt-drivers-lpspi = { workspace = true }
+imxrt-drivers-pit = { workspace = true }
+imxrt-drivers-pmu-11xx = { workspace = true }
+imxrt-drivers-rtwdog = { workspace = true }
diff --git a/chips/imxrt1160/build.rs b/chips/imxrt1160/build.rs
new file mode 100644
index 0000000..c481462
--- /dev/null
+++ b/chips/imxrt1160/build.rs
@@ -0,0 +1,8 @@
+use std::{env, fs, path};
+
+fn main() {
+    let out_dir = path::PathBuf::from(env::var("OUT_DIR").unwrap());
+    fs::copy("device.x", out_dir.join("device.x")).unwrap();
+    fs::copy("device.x", out_dir.join("imxrt1160.x")).unwrap();
+    println!("cargo::rustc-link-search={}", out_dir.display());
+}
diff --git a/chips/imxrt1160/device.x b/chips/imxrt1160/device.x
new file mode 100644
index 0000000..0ee25c3
--- /dev/null
+++ b/chips/imxrt1160/device.x
@@ -0,0 +1,194 @@
+PROVIDE(DMA0_DMA16 = DefaultHandler);
+PROVIDE(DMA1_DMA17 = DefaultHandler);
+PROVIDE(DMA2_DMA18 = DefaultHandler);
+PROVIDE(DMA3_DMA19 = DefaultHandler);
+PROVIDE(DMA4_DMA20 = DefaultHandler);
+PROVIDE(DMA5_DMA21 = DefaultHandler);
+PROVIDE(DMA6_DMA22 = DefaultHandler);
+PROVIDE(DMA7_DMA23 = DefaultHandler);
+PROVIDE(DMA8_DMA24 = DefaultHandler);
+PROVIDE(DMA9_DMA25 = DefaultHandler);
+PROVIDE(DMA10_DMA26 = DefaultHandler);
+PROVIDE(DMA11_DMA27 = DefaultHandler);
+PROVIDE(DMA12_DMA28 = DefaultHandler);
+PROVIDE(DMA13_DMA29 = DefaultHandler);
+PROVIDE(DMA14_DMA30 = DefaultHandler);
+PROVIDE(DMA15_DMA31 = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(CTI_TRIGGER_OUT0 = DefaultHandler);
+PROVIDE(CTI_TRIGGER_OUT1 = DefaultHandler);
+PROVIDE(CORE = DefaultHandler);
+PROVIDE(LPUART1 = DefaultHandler);
+PROVIDE(LPUART2 = DefaultHandler);
+PROVIDE(LPUART3 = DefaultHandler);
+PROVIDE(LPUART4 = DefaultHandler);
+PROVIDE(LPUART5 = DefaultHandler);
+PROVIDE(LPUART6 = DefaultHandler);
+PROVIDE(LPUART7 = DefaultHandler);
+PROVIDE(LPUART8 = DefaultHandler);
+PROVIDE(LPUART9 = DefaultHandler);
+PROVIDE(LPUART10 = DefaultHandler);
+PROVIDE(LPUART11 = DefaultHandler);
+PROVIDE(LPUART12 = DefaultHandler);
+PROVIDE(LPI2C1 = DefaultHandler);
+PROVIDE(LPI2C2 = DefaultHandler);
+PROVIDE(LPI2C3 = DefaultHandler);
+PROVIDE(LPI2C4 = DefaultHandler);
+PROVIDE(LPI2C5 = DefaultHandler);
+PROVIDE(LPI2C6 = DefaultHandler);
+PROVIDE(LPSPI1 = DefaultHandler);
+PROVIDE(LPSPI2 = DefaultHandler);
+PROVIDE(LPSPI3 = DefaultHandler);
+PROVIDE(LPSPI4 = DefaultHandler);
+PROVIDE(LPSPI5 = DefaultHandler);
+PROVIDE(LPSPI6 = DefaultHandler);
+PROVIDE(CAN1 = DefaultHandler);
+PROVIDE(CAN1_ERROR = DefaultHandler);
+PROVIDE(CAN2 = DefaultHandler);
+PROVIDE(CAN2_ERROR = DefaultHandler);
+PROVIDE(CAN3 = DefaultHandler);
+PROVIDE(CAN3_ERROR = DefaultHandler);
+PROVIDE(FLEXRAM = DefaultHandler);
+PROVIDE(KPP = DefaultHandler);
+PROVIDE(GPR_IRQ = DefaultHandler);
+PROVIDE(ELCDIF = DefaultHandler);
+PROVIDE(LCDIFV2 = DefaultHandler);
+PROVIDE(CSI = DefaultHandler);
+PROVIDE(PXP = DefaultHandler);
+PROVIDE(MIPI_CSI = DefaultHandler);
+PROVIDE(MIPI_DSI = DefaultHandler);
+PROVIDE(GPIO6_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO6_COMBINED_16_31 = DefaultHandler);
+PROVIDE(DAC = DefaultHandler);
+PROVIDE(KEY_MANAGER = DefaultHandler);
+PROVIDE(WDOG2 = DefaultHandler);
+PROVIDE(SNVS_HP_NON_TZ = DefaultHandler);
+PROVIDE(SNVS_HP_TZ = DefaultHandler);
+PROVIDE(SNVS_PULSE_EVENT = DefaultHandler);
+PROVIDE(CAAM_IRQ0 = DefaultHandler);
+PROVIDE(CAAM_IRQ1 = DefaultHandler);
+PROVIDE(CAAM_IRQ2 = DefaultHandler);
+PROVIDE(CAAM_IRQ3 = DefaultHandler);
+PROVIDE(CAAM_RECORVE_ERRPR = DefaultHandler);
+PROVIDE(CAAM_RTIC = DefaultHandler);
+PROVIDE(CDOG = DefaultHandler);
+PROVIDE(SAI1 = DefaultHandler);
+PROVIDE(SAI2 = DefaultHandler);
+PROVIDE(SAI3_RX = DefaultHandler);
+PROVIDE(SAI3_TX = DefaultHandler);
+PROVIDE(SAI4_RX = DefaultHandler);
+PROVIDE(SAI4_TX = DefaultHandler);
+PROVIDE(SPDIF = DefaultHandler);
+PROVIDE(TMPSNS_INT = DefaultHandler);
+PROVIDE(TMPSNS_LOW_HIGH = DefaultHandler);
+PROVIDE(TMPSNS_PANIC = DefaultHandler);
+PROVIDE(LPSR_LP8_BROWNOUT = DefaultHandler);
+PROVIDE(LPSR_LP0_BROWNOUT = DefaultHandler);
+PROVIDE(ADC1 = DefaultHandler);
+PROVIDE(ADC2 = DefaultHandler);
+PROVIDE(USBPHY1 = DefaultHandler);
+PROVIDE(USBPHY2 = DefaultHandler);
+PROVIDE(RDC = DefaultHandler);
+PROVIDE(GPIO13_COMBINED_0_31 = DefaultHandler);
+PROVIDE(DCIC1 = DefaultHandler);
+PROVIDE(DCIC2 = DefaultHandler);
+PROVIDE(ASRC = DefaultHandler);
+PROVIDE(FLEXRAM_ECC = DefaultHandler);
+PROVIDE(CM7_GPIO2_3 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO3_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO3_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO4_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO4_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_16_31 = DefaultHandler);
+PROVIDE(FLEXIO1 = DefaultHandler);
+PROVIDE(FLEXIO2 = DefaultHandler);
+PROVIDE(WDOG1 = DefaultHandler);
+PROVIDE(RTWDOG3 = DefaultHandler);
+PROVIDE(EWM = DefaultHandler);
+PROVIDE(OCOTP_READ_FUSE_ERROR = DefaultHandler);
+PROVIDE(OCOTP_READ_DONE_ERROR = DefaultHandler);
+PROVIDE(GPC = DefaultHandler);
+PROVIDE(MUA = DefaultHandler);
+PROVIDE(GPT1 = DefaultHandler);
+PROVIDE(GPT2 = DefaultHandler);
+PROVIDE(GPT3 = DefaultHandler);
+PROVIDE(GPT4 = DefaultHandler);
+PROVIDE(GPT5 = DefaultHandler);
+PROVIDE(GPT6 = DefaultHandler);
+PROVIDE(PWM1_0 = DefaultHandler);
+PROVIDE(PWM1_1 = DefaultHandler);
+PROVIDE(PWM1_2 = DefaultHandler);
+PROVIDE(PWM1_3 = DefaultHandler);
+PROVIDE(PWM1_FAULT = DefaultHandler);
+PROVIDE(FLEXSPI1 = DefaultHandler);
+PROVIDE(FLEXSPI2 = DefaultHandler);
+PROVIDE(SEMC = DefaultHandler);
+PROVIDE(USDHC1 = DefaultHandler);
+PROVIDE(USDHC2 = DefaultHandler);
+PROVIDE(USB_OTG2 = DefaultHandler);
+PROVIDE(USB_OTG1 = DefaultHandler);
+PROVIDE(ENET = DefaultHandler);
+PROVIDE(ENET_1588_TIMER = DefaultHandler);
+PROVIDE(ENET_1G_MAC0_TX_RX_1 = DefaultHandler);
+PROVIDE(ENET_1G_MAC0_TX_RX_2 = DefaultHandler);
+PROVIDE(ENET_1G = DefaultHandler);
+PROVIDE(ENET_1G_1588_TIMER = DefaultHandler);
+PROVIDE(XBAR1_IRQ_0_1 = DefaultHandler);
+PROVIDE(XBAR1_IRQ_2_3 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ0 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ1 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ2 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ3 = DefaultHandler);
+PROVIDE(ADC_ETC_ERROR_IRQ = DefaultHandler);
+PROVIDE(PIT1 = DefaultHandler);
+PROVIDE(PIT2 = DefaultHandler);
+PROVIDE(ACMP1 = DefaultHandler);
+PROVIDE(ACMP2 = DefaultHandler);
+PROVIDE(ACMP3 = DefaultHandler);
+PROVIDE(ACMP4 = DefaultHandler);
+PROVIDE(ENC1 = DefaultHandler);
+PROVIDE(ENC2 = DefaultHandler);
+PROVIDE(ENC3 = DefaultHandler);
+PROVIDE(ENC4 = DefaultHandler);
+PROVIDE(TMR1 = DefaultHandler);
+PROVIDE(TMR2 = DefaultHandler);
+PROVIDE(TMR3 = DefaultHandler);
+PROVIDE(TMR4 = DefaultHandler);
+PROVIDE(SEMA4_CP0 = DefaultHandler);
+PROVIDE(SEMA4_CP1 = DefaultHandler);
+PROVIDE(PWM2_0 = DefaultHandler);
+PROVIDE(PWM2_1 = DefaultHandler);
+PROVIDE(PWM2_2 = DefaultHandler);
+PROVIDE(PWM2_3 = DefaultHandler);
+PROVIDE(PWM2_FAULT = DefaultHandler);
+PROVIDE(PWM3_0 = DefaultHandler);
+PROVIDE(PWM3_1 = DefaultHandler);
+PROVIDE(PWM3_2 = DefaultHandler);
+PROVIDE(PWM3_3 = DefaultHandler);
+PROVIDE(PWM3_FAULT = DefaultHandler);
+PROVIDE(PWM4_0 = DefaultHandler);
+PROVIDE(PWM4_1 = DefaultHandler);
+PROVIDE(PWM4_2 = DefaultHandler);
+PROVIDE(PWM4_3 = DefaultHandler);
+PROVIDE(PWM4_FAULT = DefaultHandler);
+PROVIDE(PDM_HWVAD_EVENT = DefaultHandler);
+PROVIDE(PDM_HWVAD_ERROR = DefaultHandler);
+PROVIDE(PDM_EVENT = DefaultHandler);
+PROVIDE(PDM_ERROR = DefaultHandler);
+PROVIDE(EMVSIM1 = DefaultHandler);
+PROVIDE(EMVSIM2 = DefaultHandler);
+PROVIDE(MECC1_INT = DefaultHandler);
+PROVIDE(MECC1_FATAL_INT = DefaultHandler);
+PROVIDE(MECC2_INT = DefaultHandler);
+PROVIDE(MECC2_FATAL_INT = DefaultHandler);
+PROVIDE(XECC_FLEXSPI1_INT = DefaultHandler);
+PROVIDE(XECC_FLEXSPI1_FATAL_INT = DefaultHandler);
+PROVIDE(XECC_FLEXSPI2_INT = DefaultHandler);
+PROVIDE(XECC_FLEXSPI2_FATAL_INT = DefaultHandler);
+PROVIDE(XECC_SEMC_INT = DefaultHandler);
+PROVIDE(XECC_SEMC_FATAL_INT = DefaultHandler);
diff --git a/chips/imxrt1160/src/lib.rs b/chips/imxrt1160/src/lib.rs
new file mode 100644
index 0000000..d018052
--- /dev/null
+++ b/chips/imxrt1160/src/lib.rs
@@ -0,0 +1,90 @@
+#![no_std]
+
+mod rt;
+pub use rt::*;
+
+pub use imxrt_drivers_ccm_11xx::ral_11xx as ccm;
+pub use imxrt_drivers_enet as enet;
+pub use imxrt_drivers_flexspi as flexspi;
+pub use imxrt_drivers_gpio as gpio;
+pub use imxrt_drivers_iomuxc_11xx::{iomuxc, iomuxc_gpr, iomuxc_lpsr};
+pub use imxrt_drivers_lpspi as lpspi;
+pub use imxrt_drivers_pit as pit;
+
+pub mod dma {
+    pub use imxrt_drivers_edma::dma::edma as controller;
+    pub use imxrt_drivers_edma::dmamux as mux;
+    pub use imxrt_drivers_edma::edma as channel;
+    pub use imxrt_drivers_edma::element;
+
+    pub mod events {
+        use core::num::NonZero;
+
+        pub const LPSPI_RX: NonZero<u8> = NonZero::new(36).unwrap();
+        pub const LPSPI_TX: NonZero<u8> = NonZero::new(37).unwrap();
+    }
+}
+
+pub use imxrt_drivers_gpc_11xx::cpu_mode_ctrl as gpc_cpu_mode_ctrl;
+pub use imxrt_drivers_pmu_11xx as pmu;
+pub use imxrt_drivers_rtwdog as rtwdog;
+
+pub mod instances {
+    ral_registers::instances! {
+        unsafe {
+            pub gpio1<crate::gpio::RegisterBlock> = 0x4012_c000;
+            pub gpio2<crate::gpio::RegisterBlock> = 0x4013_0000;
+            pub gpio3<crate::gpio::RegisterBlock> = 0x4013_4000;
+            pub gpio4<crate::gpio::RegisterBlock> = 0x4013_8000;
+            pub gpio5<crate::gpio::RegisterBlock> = 0x4013_c000;
+            pub gpio6<crate::gpio::RegisterBlock> = 0x4014_0000;
+            pub gpio7<crate::gpio::RegisterBlock> = 0x40c5_c000;
+            pub gpio8<crate::gpio::RegisterBlock> = 0x40c6_0000;
+            pub gpio9<crate::gpio::RegisterBlock> = 0x40c6_4000;
+            pub gpio10<crate::gpio::RegisterBlock> = 0x40c6_8000;
+            pub gpio11<crate::gpio::RegisterBlock> = 0x40c6_c000;
+            pub gpio12<crate::gpio::RegisterBlock> = 0x40c7_0000;
+            pub gpio13<crate::gpio::RegisterBlock> = 0x40ca_0000;
+            pub cm7_gpio2<crate::gpio::RegisterBlock> = 0x4200_8000;
+            pub cm7_gpio3<crate::gpio::RegisterBlock> = 0x4200_c000;
+
+            pub ccm<crate::ccm::RegisterBlock> = 0x40CC_0000;
+
+            pub enet<crate::enet::RegisterBlock> = 0x4042_4000;
+            pub enet_1g<crate::enet::RegisterBlock> = 0x4042_0000;
+
+            pub flexspi1<crate::flexspi::RegisterBlock> = 0x400C_C000;
+            pub flexspi2<crate::flexspi::RegisterBlock> = 0x400D_0000;
+
+            pub iomuxc<crate::iomuxc::RegisterBlock> = 0x400E_8000;
+            pub iomuxc_gpr<crate::iomuxc_gpr::RegisterBlock> = 0x400E_4000;
+            pub iomuxc_lpsr<crate::iomuxc_lpsr::RegisterBlock> = 0x40C0_8000;
+
+            pub pit1<crate::pit::RegisterBlock> = 0x400d_8000;
+            pub pit2<crate::pit::RegisterBlock> = 0x40cb_0000;
+
+            pub lpspi1<crate::lpspi::RegisterBlock> = 0x4011_4000;
+            pub lpspi2<crate::lpspi::RegisterBlock> = 0x4011_8000;
+            pub lpspi3<crate::lpspi::RegisterBlock> = 0x4011_c000;
+            pub lpspi4<crate::lpspi::RegisterBlock> = 0x4012_0000;
+            pub lpspi5<crate::lpspi::RegisterBlock> = 0x40c2_c000;
+            pub lpspi6<crate::lpspi::RegisterBlock> = 0x40c3_0000;
+
+            pub dmamux0<crate::dma::mux::RegisterBlock> = 0x4007_4000;
+            pub dmamux1<crate::dma::mux::RegisterBlock> = 0x40C1_8000;
+
+            pub dma0<crate::dma::controller::RegisterBlock> = 0x4007_0000;
+            pub dma1<crate::dma::controller::RegisterBlock> = 0x40C1_4000;
+
+            pub gpc_cpu_mode_ctrl0<crate::gpc_cpu_mode_ctrl::RegisterBlock> = 0x40C0_0000;
+            pub gpc_cpu_mode_ctrl1<crate::gpc_cpu_mode_ctrl::RegisterBlock> = 0x40C0_0800;
+
+            pub pmu<crate::pmu::RegisterBlock> = 0x40C8_4000;
+
+            pub pll<crate::ccm::pll::RegisterBlock> = 0x40C8_4000;
+
+            pub wdog3<crate::rtwdog::RegisterBlock> = 0x4003_8000;
+            pub wdog4<crate::rtwdog::RegisterBlock> = 0x40C1_0000;
+        }
+    }
+}
diff --git a/chips/imxrt1160/src/rt.rs b/chips/imxrt1160/src/rt.rs
new file mode 100644
index 0000000..b132926
--- /dev/null
+++ b/chips/imxrt1160/src/rt.rs
@@ -0,0 +1,993 @@
+#![allow(non_camel_case_types)]
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - DMA0_DMA16"]
+    DMA0_DMA16 = 0,
+    #[doc = "1 - DMA1_DMA17"]
+    DMA1_DMA17 = 1,
+    #[doc = "2 - DMA2_DMA18"]
+    DMA2_DMA18 = 2,
+    #[doc = "3 - DMA3_DMA19"]
+    DMA3_DMA19 = 3,
+    #[doc = "4 - DMA4_DMA20"]
+    DMA4_DMA20 = 4,
+    #[doc = "5 - DMA5_DMA21"]
+    DMA5_DMA21 = 5,
+    #[doc = "6 - DMA6_DMA22"]
+    DMA6_DMA22 = 6,
+    #[doc = "7 - DMA7_DMA23"]
+    DMA7_DMA23 = 7,
+    #[doc = "8 - DMA8_DMA24"]
+    DMA8_DMA24 = 8,
+    #[doc = "9 - DMA9_DMA25"]
+    DMA9_DMA25 = 9,
+    #[doc = "10 - DMA10_DMA26"]
+    DMA10_DMA26 = 10,
+    #[doc = "11 - DMA11_DMA27"]
+    DMA11_DMA27 = 11,
+    #[doc = "12 - DMA12_DMA28"]
+    DMA12_DMA28 = 12,
+    #[doc = "13 - DMA13_DMA29"]
+    DMA13_DMA29 = 13,
+    #[doc = "14 - DMA14_DMA30"]
+    DMA14_DMA30 = 14,
+    #[doc = "15 - DMA15_DMA31"]
+    DMA15_DMA31 = 15,
+    #[doc = "16 - DMA_ERROR"]
+    DMA_ERROR = 16,
+    #[doc = "17 - CTI_TRIGGER_OUT0"]
+    CTI_TRIGGER_OUT0 = 17,
+    #[doc = "18 - CTI_TRIGGER_OUT1"]
+    CTI_TRIGGER_OUT1 = 18,
+    #[doc = "19 - CORE"]
+    CORE = 19,
+    #[doc = "20 - LPUART1"]
+    LPUART1 = 20,
+    #[doc = "21 - LPUART2"]
+    LPUART2 = 21,
+    #[doc = "22 - LPUART3"]
+    LPUART3 = 22,
+    #[doc = "23 - LPUART4"]
+    LPUART4 = 23,
+    #[doc = "24 - LPUART5"]
+    LPUART5 = 24,
+    #[doc = "25 - LPUART6"]
+    LPUART6 = 25,
+    #[doc = "26 - LPUART7"]
+    LPUART7 = 26,
+    #[doc = "27 - LPUART8"]
+    LPUART8 = 27,
+    #[doc = "28 - LPUART9"]
+    LPUART9 = 28,
+    #[doc = "29 - LPUART10"]
+    LPUART10 = 29,
+    #[doc = "30 - LPUART11"]
+    LPUART11 = 30,
+    #[doc = "31 - LPUART12"]
+    LPUART12 = 31,
+    #[doc = "32 - LPI2C1"]
+    LPI2C1 = 32,
+    #[doc = "33 - LPI2C2"]
+    LPI2C2 = 33,
+    #[doc = "34 - LPI2C3"]
+    LPI2C3 = 34,
+    #[doc = "35 - LPI2C4"]
+    LPI2C4 = 35,
+    #[doc = "36 - LPI2C5"]
+    LPI2C5 = 36,
+    #[doc = "37 - LPI2C6"]
+    LPI2C6 = 37,
+    #[doc = "38 - LPSPI1"]
+    LPSPI1 = 38,
+    #[doc = "39 - LPSPI2"]
+    LPSPI2 = 39,
+    #[doc = "40 - LPSPI3"]
+    LPSPI3 = 40,
+    #[doc = "41 - LPSPI4"]
+    LPSPI4 = 41,
+    #[doc = "42 - LPSPI5"]
+    LPSPI5 = 42,
+    #[doc = "43 - LPSPI6"]
+    LPSPI6 = 43,
+    #[doc = "44 - CAN1"]
+    CAN1 = 44,
+    #[doc = "45 - CAN1_ERROR"]
+    CAN1_ERROR = 45,
+    #[doc = "46 - CAN2"]
+    CAN2 = 46,
+    #[doc = "47 - CAN2_ERROR"]
+    CAN2_ERROR = 47,
+    #[doc = "48 - CAN3"]
+    CAN3 = 48,
+    #[doc = "49 - CAN3_ERROR"]
+    CAN3_ERROR = 49,
+    #[doc = "50 - FLEXRAM"]
+    FLEXRAM = 50,
+    #[doc = "51 - KPP"]
+    KPP = 51,
+    #[doc = "53 - GPR_IRQ"]
+    GPR_IRQ = 53,
+    #[doc = "54 - ELCDIF"]
+    ELCDIF = 54,
+    #[doc = "55 - LCDIFV2"]
+    LCDIFV2 = 55,
+    #[doc = "56 - CSI"]
+    CSI = 56,
+    #[doc = "57 - PXP"]
+    PXP = 57,
+    #[doc = "58 - MIPI_CSI"]
+    MIPI_CSI = 58,
+    #[doc = "59 - MIPI_DSI"]
+    MIPI_DSI = 59,
+    #[doc = "61 - GPIO6_COMBINED_0_15"]
+    GPIO6_COMBINED_0_15 = 61,
+    #[doc = "62 - GPIO6_COMBINED_16_31"]
+    GPIO6_COMBINED_16_31 = 62,
+    #[doc = "63 - DAC"]
+    DAC = 63,
+    #[doc = "64 - KEY_MANAGER"]
+    KEY_MANAGER = 64,
+    #[doc = "65 - WDOG2"]
+    WDOG2 = 65,
+    #[doc = "66 - SNVS_HP_NON_TZ"]
+    SNVS_HP_NON_TZ = 66,
+    #[doc = "67 - SNVS_HP_TZ"]
+    SNVS_HP_TZ = 67,
+    #[doc = "68 - SNVS_PULSE_EVENT"]
+    SNVS_PULSE_EVENT = 68,
+    #[doc = "69 - CAAM_IRQ0"]
+    CAAM_IRQ0 = 69,
+    #[doc = "70 - CAAM_IRQ1"]
+    CAAM_IRQ1 = 70,
+    #[doc = "71 - CAAM_IRQ2"]
+    CAAM_IRQ2 = 71,
+    #[doc = "72 - CAAM_IRQ3"]
+    CAAM_IRQ3 = 72,
+    #[doc = "73 - CAAM_RECORVE_ERRPR"]
+    CAAM_RECORVE_ERRPR = 73,
+    #[doc = "74 - CAAM_RTIC"]
+    CAAM_RTIC = 74,
+    #[doc = "75 - CDOG"]
+    CDOG = 75,
+    #[doc = "76 - SAI1"]
+    SAI1 = 76,
+    #[doc = "77 - SAI2"]
+    SAI2 = 77,
+    #[doc = "78 - SAI3_RX"]
+    SAI3_RX = 78,
+    #[doc = "79 - SAI3_TX"]
+    SAI3_TX = 79,
+    #[doc = "80 - SAI4_RX"]
+    SAI4_RX = 80,
+    #[doc = "81 - SAI4_TX"]
+    SAI4_TX = 81,
+    #[doc = "82 - SPDIF"]
+    SPDIF = 82,
+    #[doc = "83 - TMPSNS_INT"]
+    TMPSNS_INT = 83,
+    #[doc = "84 - TMPSNS_LOW_HIGH"]
+    TMPSNS_LOW_HIGH = 84,
+    #[doc = "85 - TMPSNS_PANIC"]
+    TMPSNS_PANIC = 85,
+    #[doc = "86 - LPSR_LP8_BROWNOUT"]
+    LPSR_LP8_BROWNOUT = 86,
+    #[doc = "87 - LPSR_LP0_BROWNOUT"]
+    LPSR_LP0_BROWNOUT = 87,
+    #[doc = "88 - ADC1"]
+    ADC1 = 88,
+    #[doc = "89 - ADC2"]
+    ADC2 = 89,
+    #[doc = "90 - USBPHY1"]
+    USBPHY1 = 90,
+    #[doc = "91 - USBPHY2"]
+    USBPHY2 = 91,
+    #[doc = "92 - RDC"]
+    RDC = 92,
+    #[doc = "93 - GPIO13_COMBINED_0_31"]
+    GPIO13_COMBINED_0_31 = 93,
+    #[doc = "95 - DCIC1"]
+    DCIC1 = 95,
+    #[doc = "96 - DCIC2"]
+    DCIC2 = 96,
+    #[doc = "97 - ASRC"]
+    ASRC = 97,
+    #[doc = "98 - FLEXRAM_ECC"]
+    FLEXRAM_ECC = 98,
+    #[doc = "99 - CM7_GPIO2_3"]
+    CM7_GPIO2_3 = 99,
+    #[doc = "100 - GPIO1_COMBINED_0_15"]
+    GPIO1_COMBINED_0_15 = 100,
+    #[doc = "101 - GPIO1_COMBINED_16_31"]
+    GPIO1_COMBINED_16_31 = 101,
+    #[doc = "102 - GPIO2_COMBINED_0_15"]
+    GPIO2_COMBINED_0_15 = 102,
+    #[doc = "103 - GPIO2_COMBINED_16_31"]
+    GPIO2_COMBINED_16_31 = 103,
+    #[doc = "104 - GPIO3_COMBINED_0_15"]
+    GPIO3_COMBINED_0_15 = 104,
+    #[doc = "105 - GPIO3_COMBINED_16_31"]
+    GPIO3_COMBINED_16_31 = 105,
+    #[doc = "106 - GPIO4_COMBINED_0_15"]
+    GPIO4_COMBINED_0_15 = 106,
+    #[doc = "107 - GPIO4_COMBINED_16_31"]
+    GPIO4_COMBINED_16_31 = 107,
+    #[doc = "108 - GPIO5_COMBINED_0_15"]
+    GPIO5_COMBINED_0_15 = 108,
+    #[doc = "109 - GPIO5_COMBINED_16_31"]
+    GPIO5_COMBINED_16_31 = 109,
+    #[doc = "110 - FLEXIO1"]
+    FLEXIO1 = 110,
+    #[doc = "111 - FLEXIO2"]
+    FLEXIO2 = 111,
+    #[doc = "112 - WDOG1"]
+    WDOG1 = 112,
+    #[doc = "113 - RTWDOG3"]
+    RTWDOG3 = 113,
+    #[doc = "114 - EWM"]
+    EWM = 114,
+    #[doc = "115 - OCOTP_READ_FUSE_ERROR"]
+    OCOTP_READ_FUSE_ERROR = 115,
+    #[doc = "116 - OCOTP_READ_DONE_ERROR"]
+    OCOTP_READ_DONE_ERROR = 116,
+    #[doc = "117 - GPC"]
+    GPC = 117,
+    #[doc = "118 - MUA"]
+    MUA = 118,
+    #[doc = "119 - GPT1"]
+    GPT1 = 119,
+    #[doc = "120 - GPT2"]
+    GPT2 = 120,
+    #[doc = "121 - GPT3"]
+    GPT3 = 121,
+    #[doc = "122 - GPT4"]
+    GPT4 = 122,
+    #[doc = "123 - GPT5"]
+    GPT5 = 123,
+    #[doc = "124 - GPT6"]
+    GPT6 = 124,
+    #[doc = "125 - PWM1_0"]
+    PWM1_0 = 125,
+    #[doc = "126 - PWM1_1"]
+    PWM1_1 = 126,
+    #[doc = "127 - PWM1_2"]
+    PWM1_2 = 127,
+    #[doc = "128 - PWM1_3"]
+    PWM1_3 = 128,
+    #[doc = "129 - PWM1_FAULT"]
+    PWM1_FAULT = 129,
+    #[doc = "130 - FLEXSPI1"]
+    FLEXSPI1 = 130,
+    #[doc = "131 - FLEXSPI2"]
+    FLEXSPI2 = 131,
+    #[doc = "132 - SEMC"]
+    SEMC = 132,
+    #[doc = "133 - USDHC1"]
+    USDHC1 = 133,
+    #[doc = "134 - USDHC2"]
+    USDHC2 = 134,
+    #[doc = "135 - USB_OTG2"]
+    USB_OTG2 = 135,
+    #[doc = "136 - USB_OTG1"]
+    USB_OTG1 = 136,
+    #[doc = "137 - ENET"]
+    ENET = 137,
+    #[doc = "138 - ENET_1588_TIMER"]
+    ENET_1588_TIMER = 138,
+    #[doc = "139 - ENET_1G_MAC0_TX_RX_1"]
+    ENET_1G_MAC0_TX_RX_1 = 139,
+    #[doc = "140 - ENET_1G_MAC0_TX_RX_2"]
+    ENET_1G_MAC0_TX_RX_2 = 140,
+    #[doc = "141 - ENET_1G"]
+    ENET_1G = 141,
+    #[doc = "142 - ENET_1G_1588_TIMER"]
+    ENET_1G_1588_TIMER = 142,
+    #[doc = "143 - XBAR1_IRQ_0_1"]
+    XBAR1_IRQ_0_1 = 143,
+    #[doc = "144 - XBAR1_IRQ_2_3"]
+    XBAR1_IRQ_2_3 = 144,
+    #[doc = "145 - ADC_ETC_IRQ0"]
+    ADC_ETC_IRQ0 = 145,
+    #[doc = "146 - ADC_ETC_IRQ1"]
+    ADC_ETC_IRQ1 = 146,
+    #[doc = "147 - ADC_ETC_IRQ2"]
+    ADC_ETC_IRQ2 = 147,
+    #[doc = "148 - ADC_ETC_IRQ3"]
+    ADC_ETC_IRQ3 = 148,
+    #[doc = "149 - ADC_ETC_ERROR_IRQ"]
+    ADC_ETC_ERROR_IRQ = 149,
+    #[doc = "155 - PIT1"]
+    PIT1 = 155,
+    #[doc = "156 - PIT2"]
+    PIT2 = 156,
+    #[doc = "157 - ACMP1"]
+    ACMP1 = 157,
+    #[doc = "158 - ACMP2"]
+    ACMP2 = 158,
+    #[doc = "159 - ACMP3"]
+    ACMP3 = 159,
+    #[doc = "160 - ACMP4"]
+    ACMP4 = 160,
+    #[doc = "165 - ENC1"]
+    ENC1 = 165,
+    #[doc = "166 - ENC2"]
+    ENC2 = 166,
+    #[doc = "167 - ENC3"]
+    ENC3 = 167,
+    #[doc = "168 - ENC4"]
+    ENC4 = 168,
+    #[doc = "171 - TMR1"]
+    TMR1 = 171,
+    #[doc = "172 - TMR2"]
+    TMR2 = 172,
+    #[doc = "173 - TMR3"]
+    TMR3 = 173,
+    #[doc = "174 - TMR4"]
+    TMR4 = 174,
+    #[doc = "175 - SEMA4_CP0"]
+    SEMA4_CP0 = 175,
+    #[doc = "176 - SEMA4_CP1"]
+    SEMA4_CP1 = 176,
+    #[doc = "177 - PWM2_0"]
+    PWM2_0 = 177,
+    #[doc = "178 - PWM2_1"]
+    PWM2_1 = 178,
+    #[doc = "179 - PWM2_2"]
+    PWM2_2 = 179,
+    #[doc = "180 - PWM2_3"]
+    PWM2_3 = 180,
+    #[doc = "181 - PWM2_FAULT"]
+    PWM2_FAULT = 181,
+    #[doc = "182 - PWM3_0"]
+    PWM3_0 = 182,
+    #[doc = "183 - PWM3_1"]
+    PWM3_1 = 183,
+    #[doc = "184 - PWM3_2"]
+    PWM3_2 = 184,
+    #[doc = "185 - PWM3_3"]
+    PWM3_3 = 185,
+    #[doc = "186 - PWM3_FAULT"]
+    PWM3_FAULT = 186,
+    #[doc = "187 - PWM4_0"]
+    PWM4_0 = 187,
+    #[doc = "188 - PWM4_1"]
+    PWM4_1 = 188,
+    #[doc = "189 - PWM4_2"]
+    PWM4_2 = 189,
+    #[doc = "190 - PWM4_3"]
+    PWM4_3 = 190,
+    #[doc = "191 - PWM4_FAULT"]
+    PWM4_FAULT = 191,
+    #[doc = "200 - PDM_HWVAD_EVENT"]
+    PDM_HWVAD_EVENT = 200,
+    #[doc = "201 - PDM_HWVAD_ERROR"]
+    PDM_HWVAD_ERROR = 201,
+    #[doc = "202 - PDM_EVENT"]
+    PDM_EVENT = 202,
+    #[doc = "203 - PDM_ERROR"]
+    PDM_ERROR = 203,
+    #[doc = "204 - EMVSIM1"]
+    EMVSIM1 = 204,
+    #[doc = "205 - EMVSIM2"]
+    EMVSIM2 = 205,
+    #[doc = "206 - MECC1_INT"]
+    MECC1_INT = 206,
+    #[doc = "207 - MECC1_FATAL_INT"]
+    MECC1_FATAL_INT = 207,
+    #[doc = "208 - MECC2_INT"]
+    MECC2_INT = 208,
+    #[doc = "209 - MECC2_FATAL_INT"]
+    MECC2_FATAL_INT = 209,
+    #[doc = "210 - XECC_FLEXSPI1_INT"]
+    XECC_FLEXSPI1_INT = 210,
+    #[doc = "211 - XECC_FLEXSPI1_FATAL_INT"]
+    XECC_FLEXSPI1_FATAL_INT = 211,
+    #[doc = "212 - XECC_FLEXSPI2_INT"]
+    XECC_FLEXSPI2_INT = 212,
+    #[doc = "213 - XECC_FLEXSPI2_FATAL_INT"]
+    XECC_FLEXSPI2_FATAL_INT = 213,
+    #[doc = "214 - XECC_SEMC_INT"]
+    XECC_SEMC_INT = 214,
+    #[doc = "215 - XECC_SEMC_FATAL_INT"]
+    XECC_SEMC_FATAL_INT = 215,
+}
+pub type interrupt = Interrupt;
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+
+mod _vectors {
+    unsafe extern "C" {
+        fn DMA0_DMA16();
+        fn DMA1_DMA17();
+        fn DMA2_DMA18();
+        fn DMA3_DMA19();
+        fn DMA4_DMA20();
+        fn DMA5_DMA21();
+        fn DMA6_DMA22();
+        fn DMA7_DMA23();
+        fn DMA8_DMA24();
+        fn DMA9_DMA25();
+        fn DMA10_DMA26();
+        fn DMA11_DMA27();
+        fn DMA12_DMA28();
+        fn DMA13_DMA29();
+        fn DMA14_DMA30();
+        fn DMA15_DMA31();
+        fn DMA_ERROR();
+        fn CTI_TRIGGER_OUT0();
+        fn CTI_TRIGGER_OUT1();
+        fn CORE();
+        fn LPUART1();
+        fn LPUART2();
+        fn LPUART3();
+        fn LPUART4();
+        fn LPUART5();
+        fn LPUART6();
+        fn LPUART7();
+        fn LPUART8();
+        fn LPUART9();
+        fn LPUART10();
+        fn LPUART11();
+        fn LPUART12();
+        fn LPI2C1();
+        fn LPI2C2();
+        fn LPI2C3();
+        fn LPI2C4();
+        fn LPI2C5();
+        fn LPI2C6();
+        fn LPSPI1();
+        fn LPSPI2();
+        fn LPSPI3();
+        fn LPSPI4();
+        fn LPSPI5();
+        fn LPSPI6();
+        fn CAN1();
+        fn CAN1_ERROR();
+        fn CAN2();
+        fn CAN2_ERROR();
+        fn CAN3();
+        fn CAN3_ERROR();
+        fn FLEXRAM();
+        fn KPP();
+        fn GPR_IRQ();
+        fn ELCDIF();
+        fn LCDIFV2();
+        fn CSI();
+        fn PXP();
+        fn MIPI_CSI();
+        fn MIPI_DSI();
+        fn GPIO6_COMBINED_0_15();
+        fn GPIO6_COMBINED_16_31();
+        fn DAC();
+        fn KEY_MANAGER();
+        fn WDOG2();
+        fn SNVS_HP_NON_TZ();
+        fn SNVS_HP_TZ();
+        fn SNVS_PULSE_EVENT();
+        fn CAAM_IRQ0();
+        fn CAAM_IRQ1();
+        fn CAAM_IRQ2();
+        fn CAAM_IRQ3();
+        fn CAAM_RECORVE_ERRPR();
+        fn CAAM_RTIC();
+        fn CDOG();
+        fn SAI1();
+        fn SAI2();
+        fn SAI3_RX();
+        fn SAI3_TX();
+        fn SAI4_RX();
+        fn SAI4_TX();
+        fn SPDIF();
+        fn TMPSNS_INT();
+        fn TMPSNS_LOW_HIGH();
+        fn TMPSNS_PANIC();
+        fn LPSR_LP8_BROWNOUT();
+        fn LPSR_LP0_BROWNOUT();
+        fn ADC1();
+        fn ADC2();
+        fn USBPHY1();
+        fn USBPHY2();
+        fn RDC();
+        fn GPIO13_COMBINED_0_31();
+        fn DCIC1();
+        fn DCIC2();
+        fn ASRC();
+        fn FLEXRAM_ECC();
+        fn CM7_GPIO2_3();
+        fn GPIO1_COMBINED_0_15();
+        fn GPIO1_COMBINED_16_31();
+        fn GPIO2_COMBINED_0_15();
+        fn GPIO2_COMBINED_16_31();
+        fn GPIO3_COMBINED_0_15();
+        fn GPIO3_COMBINED_16_31();
+        fn GPIO4_COMBINED_0_15();
+        fn GPIO4_COMBINED_16_31();
+        fn GPIO5_COMBINED_0_15();
+        fn GPIO5_COMBINED_16_31();
+        fn FLEXIO1();
+        fn FLEXIO2();
+        fn WDOG1();
+        fn RTWDOG3();
+        fn EWM();
+        fn OCOTP_READ_FUSE_ERROR();
+        fn OCOTP_READ_DONE_ERROR();
+        fn GPC();
+        fn MUA();
+        fn GPT1();
+        fn GPT2();
+        fn GPT3();
+        fn GPT4();
+        fn GPT5();
+        fn GPT6();
+        fn PWM1_0();
+        fn PWM1_1();
+        fn PWM1_2();
+        fn PWM1_3();
+        fn PWM1_FAULT();
+        fn FLEXSPI1();
+        fn FLEXSPI2();
+        fn SEMC();
+        fn USDHC1();
+        fn USDHC2();
+        fn USB_OTG2();
+        fn USB_OTG1();
+        fn ENET();
+        fn ENET_1588_TIMER();
+        fn ENET_1G_MAC0_TX_RX_1();
+        fn ENET_1G_MAC0_TX_RX_2();
+        fn ENET_1G();
+        fn ENET_1G_1588_TIMER();
+        fn XBAR1_IRQ_0_1();
+        fn XBAR1_IRQ_2_3();
+        fn ADC_ETC_IRQ0();
+        fn ADC_ETC_IRQ1();
+        fn ADC_ETC_IRQ2();
+        fn ADC_ETC_IRQ3();
+        fn ADC_ETC_ERROR_IRQ();
+        fn PIT1();
+        fn PIT2();
+        fn ACMP1();
+        fn ACMP2();
+        fn ACMP3();
+        fn ACMP4();
+        fn ENC1();
+        fn ENC2();
+        fn ENC3();
+        fn ENC4();
+        fn TMR1();
+        fn TMR2();
+        fn TMR3();
+        fn TMR4();
+        fn SEMA4_CP0();
+        fn SEMA4_CP1();
+        fn PWM2_0();
+        fn PWM2_1();
+        fn PWM2_2();
+        fn PWM2_3();
+        fn PWM2_FAULT();
+        fn PWM3_0();
+        fn PWM3_1();
+        fn PWM3_2();
+        fn PWM3_3();
+        fn PWM3_FAULT();
+        fn PWM4_0();
+        fn PWM4_1();
+        fn PWM4_2();
+        fn PWM4_3();
+        fn PWM4_FAULT();
+        fn PDM_HWVAD_EVENT();
+        fn PDM_HWVAD_ERROR();
+        fn PDM_EVENT();
+        fn PDM_ERROR();
+        fn EMVSIM1();
+        fn EMVSIM2();
+        fn MECC1_INT();
+        fn MECC1_FATAL_INT();
+        fn MECC2_INT();
+        fn MECC2_FATAL_INT();
+        fn XECC_FLEXSPI1_INT();
+        fn XECC_FLEXSPI1_FATAL_INT();
+        fn XECC_FLEXSPI2_INT();
+        fn XECC_FLEXSPI2_FATAL_INT();
+        fn XECC_SEMC_INT();
+        fn XECC_SEMC_FATAL_INT();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".vector_table.interrupts"))]
+    #[unsafe(no_mangle)]
+    pub static __INTERRUPTS: [Vector; 216] = [
+        Vector {
+            _handler: DMA0_DMA16,
+        },
+        Vector {
+            _handler: DMA1_DMA17,
+        },
+        Vector {
+            _handler: DMA2_DMA18,
+        },
+        Vector {
+            _handler: DMA3_DMA19,
+        },
+        Vector {
+            _handler: DMA4_DMA20,
+        },
+        Vector {
+            _handler: DMA5_DMA21,
+        },
+        Vector {
+            _handler: DMA6_DMA22,
+        },
+        Vector {
+            _handler: DMA7_DMA23,
+        },
+        Vector {
+            _handler: DMA8_DMA24,
+        },
+        Vector {
+            _handler: DMA9_DMA25,
+        },
+        Vector {
+            _handler: DMA10_DMA26,
+        },
+        Vector {
+            _handler: DMA11_DMA27,
+        },
+        Vector {
+            _handler: DMA12_DMA28,
+        },
+        Vector {
+            _handler: DMA13_DMA29,
+        },
+        Vector {
+            _handler: DMA14_DMA30,
+        },
+        Vector {
+            _handler: DMA15_DMA31,
+        },
+        Vector {
+            _handler: DMA_ERROR,
+        },
+        Vector {
+            _handler: CTI_TRIGGER_OUT0,
+        },
+        Vector {
+            _handler: CTI_TRIGGER_OUT1,
+        },
+        Vector { _handler: CORE },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: LPUART2 },
+        Vector { _handler: LPUART3 },
+        Vector { _handler: LPUART4 },
+        Vector { _handler: LPUART5 },
+        Vector { _handler: LPUART6 },
+        Vector { _handler: LPUART7 },
+        Vector { _handler: LPUART8 },
+        Vector { _handler: LPUART9 },
+        Vector { _handler: LPUART10 },
+        Vector { _handler: LPUART11 },
+        Vector { _handler: LPUART12 },
+        Vector { _handler: LPI2C1 },
+        Vector { _handler: LPI2C2 },
+        Vector { _handler: LPI2C3 },
+        Vector { _handler: LPI2C4 },
+        Vector { _handler: LPI2C5 },
+        Vector { _handler: LPI2C6 },
+        Vector { _handler: LPSPI1 },
+        Vector { _handler: LPSPI2 },
+        Vector { _handler: LPSPI3 },
+        Vector { _handler: LPSPI4 },
+        Vector { _handler: LPSPI5 },
+        Vector { _handler: LPSPI6 },
+        Vector { _handler: CAN1 },
+        Vector {
+            _handler: CAN1_ERROR,
+        },
+        Vector { _handler: CAN2 },
+        Vector {
+            _handler: CAN2_ERROR,
+        },
+        Vector { _handler: CAN3 },
+        Vector {
+            _handler: CAN3_ERROR,
+        },
+        Vector { _handler: FLEXRAM },
+        Vector { _handler: KPP },
+        Vector { _reserved: 0 },
+        Vector { _handler: GPR_IRQ },
+        Vector { _handler: ELCDIF },
+        Vector { _handler: LCDIFV2 },
+        Vector { _handler: CSI },
+        Vector { _handler: PXP },
+        Vector { _handler: MIPI_CSI },
+        Vector { _handler: MIPI_DSI },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: GPIO6_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO6_COMBINED_16_31,
+        },
+        Vector { _handler: DAC },
+        Vector {
+            _handler: KEY_MANAGER,
+        },
+        Vector { _handler: WDOG2 },
+        Vector {
+            _handler: SNVS_HP_NON_TZ,
+        },
+        Vector {
+            _handler: SNVS_HP_TZ,
+        },
+        Vector {
+            _handler: SNVS_PULSE_EVENT,
+        },
+        Vector {
+            _handler: CAAM_IRQ0,
+        },
+        Vector {
+            _handler: CAAM_IRQ1,
+        },
+        Vector {
+            _handler: CAAM_IRQ2,
+        },
+        Vector {
+            _handler: CAAM_IRQ3,
+        },
+        Vector {
+            _handler: CAAM_RECORVE_ERRPR,
+        },
+        Vector {
+            _handler: CAAM_RTIC,
+        },
+        Vector { _handler: CDOG },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SAI3_RX },
+        Vector { _handler: SAI3_TX },
+        Vector { _handler: SAI4_RX },
+        Vector { _handler: SAI4_TX },
+        Vector { _handler: SPDIF },
+        Vector {
+            _handler: TMPSNS_INT,
+        },
+        Vector {
+            _handler: TMPSNS_LOW_HIGH,
+        },
+        Vector {
+            _handler: TMPSNS_PANIC,
+        },
+        Vector {
+            _handler: LPSR_LP8_BROWNOUT,
+        },
+        Vector {
+            _handler: LPSR_LP0_BROWNOUT,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: ADC2 },
+        Vector { _handler: USBPHY1 },
+        Vector { _handler: USBPHY2 },
+        Vector { _handler: RDC },
+        Vector {
+            _handler: GPIO13_COMBINED_0_31,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: DCIC1 },
+        Vector { _handler: DCIC2 },
+        Vector { _handler: ASRC },
+        Vector {
+            _handler: FLEXRAM_ECC,
+        },
+        Vector {
+            _handler: CM7_GPIO2_3,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_16_31,
+        },
+        Vector { _handler: FLEXIO1 },
+        Vector { _handler: FLEXIO2 },
+        Vector { _handler: WDOG1 },
+        Vector { _handler: RTWDOG3 },
+        Vector { _handler: EWM },
+        Vector {
+            _handler: OCOTP_READ_FUSE_ERROR,
+        },
+        Vector {
+            _handler: OCOTP_READ_DONE_ERROR,
+        },
+        Vector { _handler: GPC },
+        Vector { _handler: MUA },
+        Vector { _handler: GPT1 },
+        Vector { _handler: GPT2 },
+        Vector { _handler: GPT3 },
+        Vector { _handler: GPT4 },
+        Vector { _handler: GPT5 },
+        Vector { _handler: GPT6 },
+        Vector { _handler: PWM1_0 },
+        Vector { _handler: PWM1_1 },
+        Vector { _handler: PWM1_2 },
+        Vector { _handler: PWM1_3 },
+        Vector {
+            _handler: PWM1_FAULT,
+        },
+        Vector { _handler: FLEXSPI1 },
+        Vector { _handler: FLEXSPI2 },
+        Vector { _handler: SEMC },
+        Vector { _handler: USDHC1 },
+        Vector { _handler: USDHC2 },
+        Vector { _handler: USB_OTG2 },
+        Vector { _handler: USB_OTG1 },
+        Vector { _handler: ENET },
+        Vector {
+            _handler: ENET_1588_TIMER,
+        },
+        Vector {
+            _handler: ENET_1G_MAC0_TX_RX_1,
+        },
+        Vector {
+            _handler: ENET_1G_MAC0_TX_RX_2,
+        },
+        Vector { _handler: ENET_1G },
+        Vector {
+            _handler: ENET_1G_1588_TIMER,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_0_1,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_2_3,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ0,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ1,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ2,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ3,
+        },
+        Vector {
+            _handler: ADC_ETC_ERROR_IRQ,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: PIT1 },
+        Vector { _handler: PIT2 },
+        Vector { _handler: ACMP1 },
+        Vector { _handler: ACMP2 },
+        Vector { _handler: ACMP3 },
+        Vector { _handler: ACMP4 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: ENC1 },
+        Vector { _handler: ENC2 },
+        Vector { _handler: ENC3 },
+        Vector { _handler: ENC4 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TMR1 },
+        Vector { _handler: TMR2 },
+        Vector { _handler: TMR3 },
+        Vector { _handler: TMR4 },
+        Vector {
+            _handler: SEMA4_CP0,
+        },
+        Vector {
+            _handler: SEMA4_CP1,
+        },
+        Vector { _handler: PWM2_0 },
+        Vector { _handler: PWM2_1 },
+        Vector { _handler: PWM2_2 },
+        Vector { _handler: PWM2_3 },
+        Vector {
+            _handler: PWM2_FAULT,
+        },
+        Vector { _handler: PWM3_0 },
+        Vector { _handler: PWM3_1 },
+        Vector { _handler: PWM3_2 },
+        Vector { _handler: PWM3_3 },
+        Vector {
+            _handler: PWM3_FAULT,
+        },
+        Vector { _handler: PWM4_0 },
+        Vector { _handler: PWM4_1 },
+        Vector { _handler: PWM4_2 },
+        Vector { _handler: PWM4_3 },
+        Vector {
+            _handler: PWM4_FAULT,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: PDM_HWVAD_EVENT,
+        },
+        Vector {
+            _handler: PDM_HWVAD_ERROR,
+        },
+        Vector {
+            _handler: PDM_EVENT,
+        },
+        Vector {
+            _handler: PDM_ERROR,
+        },
+        Vector { _handler: EMVSIM1 },
+        Vector { _handler: EMVSIM2 },
+        Vector {
+            _handler: MECC1_INT,
+        },
+        Vector {
+            _handler: MECC1_FATAL_INT,
+        },
+        Vector {
+            _handler: MECC2_INT,
+        },
+        Vector {
+            _handler: MECC2_FATAL_INT,
+        },
+        Vector {
+            _handler: XECC_FLEXSPI1_INT,
+        },
+        Vector {
+            _handler: XECC_FLEXSPI1_FATAL_INT,
+        },
+        Vector {
+            _handler: XECC_FLEXSPI2_INT,
+        },
+        Vector {
+            _handler: XECC_FLEXSPI2_FATAL_INT,
+        },
+        Vector {
+            _handler: XECC_SEMC_INT,
+        },
+        Vector {
+            _handler: XECC_SEMC_FATAL_INT,
+        },
+    ];
+}
diff --git a/chips/imxrt1170/Cargo.toml b/chips/imxrt1170/Cargo.toml
new file mode 100644
index 0000000..58cf385
--- /dev/null
+++ b/chips/imxrt1170/Cargo.toml
@@ -0,0 +1,19 @@
+[package]
+name = "imxrt1170"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+cortex-m = { workspace = true }
+ral-registers = { workspace = true }
+
+imxrt-drivers-ccm-11xx = { workspace = true }
+imxrt-drivers-enet = { workspace = true }
+imxrt-drivers-flexspi = { workspace = true }
+imxrt-drivers-gpio = { workspace = true }
+imxrt-drivers-gpc-11xx = { workspace = true }
+imxrt-drivers-iomuxc-11xx = { workspace = true }
+imxrt-drivers-lpspi= { workspace = true }
+imxrt-drivers-pit = { workspace = true }
+imxrt-drivers-pmu-11xx = { workspace = true }
+imxrt-drivers-rtwdog = { workspace = true }
diff --git a/chips/imxrt1170/build.rs b/chips/imxrt1170/build.rs
new file mode 100644
index 0000000..fce38fb
--- /dev/null
+++ b/chips/imxrt1170/build.rs
@@ -0,0 +1,8 @@
+use std::{env, fs, path};
+
+fn main() {
+    let out_dir = path::PathBuf::from(env::var("OUT_DIR").unwrap());
+    fs::copy("device.x", out_dir.join("device.x")).unwrap();
+    fs::copy("device.x", out_dir.join("imxrt1170.x")).unwrap();
+    println!("cargo::rustc-link-search={}", out_dir.display());
+}
diff --git a/chips/imxrt1170/device.x b/chips/imxrt1170/device.x
new file mode 100644
index 0000000..4b9276e
--- /dev/null
+++ b/chips/imxrt1170/device.x
@@ -0,0 +1,196 @@
+PROVIDE(DMA0_DMA16 = DefaultHandler);
+PROVIDE(DMA1_DMA17 = DefaultHandler);
+PROVIDE(DMA2_DMA18 = DefaultHandler);
+PROVIDE(DMA3_DMA19 = DefaultHandler);
+PROVIDE(DMA4_DMA20 = DefaultHandler);
+PROVIDE(DMA5_DMA21 = DefaultHandler);
+PROVIDE(DMA6_DMA22 = DefaultHandler);
+PROVIDE(DMA7_DMA23 = DefaultHandler);
+PROVIDE(DMA8_DMA24 = DefaultHandler);
+PROVIDE(DMA9_DMA25 = DefaultHandler);
+PROVIDE(DMA10_DMA26 = DefaultHandler);
+PROVIDE(DMA11_DMA27 = DefaultHandler);
+PROVIDE(DMA12_DMA28 = DefaultHandler);
+PROVIDE(DMA13_DMA29 = DefaultHandler);
+PROVIDE(DMA14_DMA30 = DefaultHandler);
+PROVIDE(DMA15_DMA31 = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(CTI_TRIGGER_OUT0 = DefaultHandler);
+PROVIDE(CTI_TRIGGER_OUT1 = DefaultHandler);
+PROVIDE(CORE = DefaultHandler);
+PROVIDE(LPUART1 = DefaultHandler);
+PROVIDE(LPUART2 = DefaultHandler);
+PROVIDE(LPUART3 = DefaultHandler);
+PROVIDE(LPUART4 = DefaultHandler);
+PROVIDE(LPUART5 = DefaultHandler);
+PROVIDE(LPUART6 = DefaultHandler);
+PROVIDE(LPUART7 = DefaultHandler);
+PROVIDE(LPUART8 = DefaultHandler);
+PROVIDE(LPUART9 = DefaultHandler);
+PROVIDE(LPUART10 = DefaultHandler);
+PROVIDE(LPUART11 = DefaultHandler);
+PROVIDE(LPUART12 = DefaultHandler);
+PROVIDE(LPI2C1 = DefaultHandler);
+PROVIDE(LPI2C2 = DefaultHandler);
+PROVIDE(LPI2C3 = DefaultHandler);
+PROVIDE(LPI2C4 = DefaultHandler);
+PROVIDE(LPI2C5 = DefaultHandler);
+PROVIDE(LPI2C6 = DefaultHandler);
+PROVIDE(LPSPI1 = DefaultHandler);
+PROVIDE(LPSPI2 = DefaultHandler);
+PROVIDE(LPSPI3 = DefaultHandler);
+PROVIDE(LPSPI4 = DefaultHandler);
+PROVIDE(LPSPI5 = DefaultHandler);
+PROVIDE(LPSPI6 = DefaultHandler);
+PROVIDE(CAN1 = DefaultHandler);
+PROVIDE(CAN1_ERROR = DefaultHandler);
+PROVIDE(CAN2 = DefaultHandler);
+PROVIDE(CAN2_ERROR = DefaultHandler);
+PROVIDE(CAN3 = DefaultHandler);
+PROVIDE(CAN3_ERROR = DefaultHandler);
+PROVIDE(FLEXRAM = DefaultHandler);
+PROVIDE(KPP = DefaultHandler);
+PROVIDE(GPR_IRQ = DefaultHandler);
+PROVIDE(ELCDIF = DefaultHandler);
+PROVIDE(LCDIFV2 = DefaultHandler);
+PROVIDE(CSI = DefaultHandler);
+PROVIDE(PXP = DefaultHandler);
+PROVIDE(MIPI_CSI = DefaultHandler);
+PROVIDE(MIPI_DSI = DefaultHandler);
+PROVIDE(GPIO6_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO6_COMBINED_16_31 = DefaultHandler);
+PROVIDE(DAC = DefaultHandler);
+PROVIDE(KEY_MANAGER = DefaultHandler);
+PROVIDE(WDOG2 = DefaultHandler);
+PROVIDE(SNVS_HP_NON_TZ = DefaultHandler);
+PROVIDE(SNVS_HP_TZ = DefaultHandler);
+PROVIDE(SNVS_PULSE_EVENT = DefaultHandler);
+PROVIDE(CAAM_IRQ0 = DefaultHandler);
+PROVIDE(CAAM_IRQ1 = DefaultHandler);
+PROVIDE(CAAM_IRQ2 = DefaultHandler);
+PROVIDE(CAAM_IRQ3 = DefaultHandler);
+PROVIDE(CAAM_RECORVE_ERRPR = DefaultHandler);
+PROVIDE(CAAM_RTIC = DefaultHandler);
+PROVIDE(CDOG = DefaultHandler);
+PROVIDE(SAI1 = DefaultHandler);
+PROVIDE(SAI2 = DefaultHandler);
+PROVIDE(SAI3_RX = DefaultHandler);
+PROVIDE(SAI3_TX = DefaultHandler);
+PROVIDE(SAI4_RX = DefaultHandler);
+PROVIDE(SAI4_TX = DefaultHandler);
+PROVIDE(SPDIF = DefaultHandler);
+PROVIDE(TMPSNS_INT = DefaultHandler);
+PROVIDE(TMPSNS_LOW_HIGH = DefaultHandler);
+PROVIDE(TMPSNS_PANIC = DefaultHandler);
+PROVIDE(LPSR_LP8_BROWNOUT = DefaultHandler);
+PROVIDE(LPSR_LP0_BROWNOUT = DefaultHandler);
+PROVIDE(ADC1 = DefaultHandler);
+PROVIDE(ADC2 = DefaultHandler);
+PROVIDE(USBPHY1 = DefaultHandler);
+PROVIDE(USBPHY2 = DefaultHandler);
+PROVIDE(RDC = DefaultHandler);
+PROVIDE(GPIO13_COMBINED_0_31 = DefaultHandler);
+PROVIDE(DCIC1 = DefaultHandler);
+PROVIDE(DCIC2 = DefaultHandler);
+PROVIDE(ASRC = DefaultHandler);
+PROVIDE(FLEXRAM_ECC = DefaultHandler);
+PROVIDE(CM7_GPIO2_3 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO3_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO3_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO4_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO4_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_16_31 = DefaultHandler);
+PROVIDE(FLEXIO1 = DefaultHandler);
+PROVIDE(FLEXIO2 = DefaultHandler);
+PROVIDE(WDOG1 = DefaultHandler);
+PROVIDE(RTWDOG3 = DefaultHandler);
+PROVIDE(EWM = DefaultHandler);
+PROVIDE(OCOTP_READ_FUSE_ERROR = DefaultHandler);
+PROVIDE(OCOTP_READ_DONE_ERROR = DefaultHandler);
+PROVIDE(GPC = DefaultHandler);
+PROVIDE(MUA = DefaultHandler);
+PROVIDE(GPT1 = DefaultHandler);
+PROVIDE(GPT2 = DefaultHandler);
+PROVIDE(GPT3 = DefaultHandler);
+PROVIDE(GPT4 = DefaultHandler);
+PROVIDE(GPT5 = DefaultHandler);
+PROVIDE(GPT6 = DefaultHandler);
+PROVIDE(PWM1_0 = DefaultHandler);
+PROVIDE(PWM1_1 = DefaultHandler);
+PROVIDE(PWM1_2 = DefaultHandler);
+PROVIDE(PWM1_3 = DefaultHandler);
+PROVIDE(PWM1_FAULT = DefaultHandler);
+PROVIDE(FLEXSPI1 = DefaultHandler);
+PROVIDE(FLEXSPI2 = DefaultHandler);
+PROVIDE(SEMC = DefaultHandler);
+PROVIDE(USDHC1 = DefaultHandler);
+PROVIDE(USDHC2 = DefaultHandler);
+PROVIDE(USB_OTG2 = DefaultHandler);
+PROVIDE(USB_OTG1 = DefaultHandler);
+PROVIDE(ENET = DefaultHandler);
+PROVIDE(ENET_1588_TIMER = DefaultHandler);
+PROVIDE(ENET_1G_MAC0_TX_RX_1 = DefaultHandler);
+PROVIDE(ENET_1G_MAC0_TX_RX_2 = DefaultHandler);
+PROVIDE(ENET_1G = DefaultHandler);
+PROVIDE(ENET_1G_1588_TIMER = DefaultHandler);
+PROVIDE(XBAR1_IRQ_0_1 = DefaultHandler);
+PROVIDE(XBAR1_IRQ_2_3 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ0 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ1 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ2 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ3 = DefaultHandler);
+PROVIDE(ADC_ETC_ERROR_IRQ = DefaultHandler);
+PROVIDE(PIT1 = DefaultHandler);
+PROVIDE(PIT2 = DefaultHandler);
+PROVIDE(ACMP1 = DefaultHandler);
+PROVIDE(ACMP2 = DefaultHandler);
+PROVIDE(ACMP3 = DefaultHandler);
+PROVIDE(ACMP4 = DefaultHandler);
+PROVIDE(ENC1 = DefaultHandler);
+PROVIDE(ENC2 = DefaultHandler);
+PROVIDE(ENC3 = DefaultHandler);
+PROVIDE(ENC4 = DefaultHandler);
+PROVIDE(TMR1 = DefaultHandler);
+PROVIDE(TMR2 = DefaultHandler);
+PROVIDE(TMR3 = DefaultHandler);
+PROVIDE(TMR4 = DefaultHandler);
+PROVIDE(SEMA4_CP0 = DefaultHandler);
+PROVIDE(SEMA4_CP1 = DefaultHandler);
+PROVIDE(PWM2_0 = DefaultHandler);
+PROVIDE(PWM2_1 = DefaultHandler);
+PROVIDE(PWM2_2 = DefaultHandler);
+PROVIDE(PWM2_3 = DefaultHandler);
+PROVIDE(PWM2_FAULT = DefaultHandler);
+PROVIDE(PWM3_0 = DefaultHandler);
+PROVIDE(PWM3_1 = DefaultHandler);
+PROVIDE(PWM3_2 = DefaultHandler);
+PROVIDE(PWM3_3 = DefaultHandler);
+PROVIDE(PWM3_FAULT = DefaultHandler);
+PROVIDE(PWM4_0 = DefaultHandler);
+PROVIDE(PWM4_1 = DefaultHandler);
+PROVIDE(PWM4_2 = DefaultHandler);
+PROVIDE(PWM4_3 = DefaultHandler);
+PROVIDE(PWM4_FAULT = DefaultHandler);
+PROVIDE(PDM_HWVAD_EVENT = DefaultHandler);
+PROVIDE(PDM_HWVAD_ERROR = DefaultHandler);
+PROVIDE(PDM_EVENT = DefaultHandler);
+PROVIDE(PDM_ERROR = DefaultHandler);
+PROVIDE(EMVSIM1 = DefaultHandler);
+PROVIDE(EMVSIM2 = DefaultHandler);
+PROVIDE(MECC1_INT = DefaultHandler);
+PROVIDE(MECC1_FATAL_INT = DefaultHandler);
+PROVIDE(MECC2_INT = DefaultHandler);
+PROVIDE(MECC2_FATAL_INT = DefaultHandler);
+PROVIDE(XECC_FLEXSPI1_INT = DefaultHandler);
+PROVIDE(XECC_FLEXSPI1_FATAL_INT = DefaultHandler);
+PROVIDE(XECC_FLEXSPI2_INT = DefaultHandler);
+PROVIDE(XECC_FLEXSPI2_FATAL_INT = DefaultHandler);
+PROVIDE(XECC_SEMC_INT = DefaultHandler);
+PROVIDE(XECC_SEMC_FATAL_INT = DefaultHandler);
+PROVIDE(ENET_QOS = DefaultHandler);
+PROVIDE(ENET_QOS_PMT = DefaultHandler);
diff --git a/chips/imxrt1170/src/lib.rs b/chips/imxrt1170/src/lib.rs
new file mode 100644
index 0000000..bb1c146
--- /dev/null
+++ b/chips/imxrt1170/src/lib.rs
@@ -0,0 +1,69 @@
+#![no_std]
+
+mod rt;
+pub use rt::*;
+
+pub use imxrt_drivers_ccm_11xx::ral_11xx as ccm;
+pub use imxrt_drivers_enet as enet;
+pub use imxrt_drivers_flexspi as flexspi;
+pub use imxrt_drivers_gpio as gpio;
+pub use imxrt_drivers_iomuxc_11xx::{iomuxc, iomuxc_gpr, iomuxc_lpsr};
+pub use imxrt_drivers_lpspi as lpspi;
+pub use imxrt_drivers_pit as pit;
+
+pub use imxrt_drivers_gpc_11xx::cpu_mode_ctrl as gpc_cpu_mode_ctrl;
+pub use imxrt_drivers_pmu_11xx as pmu;
+pub use imxrt_drivers_rtwdog as rtwdog;
+
+pub mod instances {
+    ral_registers::instances! {
+        unsafe {
+            pub gpio1<crate::gpio::RegisterBlock> = 0x4012_c000;
+            pub gpio2<crate::gpio::RegisterBlock> = 0x4013_0000;
+            pub gpio3<crate::gpio::RegisterBlock> = 0x4013_4000;
+            pub gpio4<crate::gpio::RegisterBlock> = 0x4013_8000;
+            pub gpio5<crate::gpio::RegisterBlock> = 0x4013_c000;
+            pub gpio6<crate::gpio::RegisterBlock> = 0x4014_0000;
+            pub gpio7<crate::gpio::RegisterBlock> = 0x40c5_c000;
+            pub gpio8<crate::gpio::RegisterBlock> = 0x40c6_0000;
+            pub gpio9<crate::gpio::RegisterBlock> = 0x40c6_4000;
+            pub gpio10<crate::gpio::RegisterBlock> = 0x40c6_8000;
+            pub gpio11<crate::gpio::RegisterBlock> = 0x40c6_c000;
+            pub gpio12<crate::gpio::RegisterBlock> = 0x40c7_0000;
+            pub gpio13<crate::gpio::RegisterBlock> = 0x40ca_0000;
+            pub cm7_gpio2<crate::gpio::RegisterBlock> = 0x4200_8000;
+            pub cm7_gpio3<crate::gpio::RegisterBlock> = 0x4200_c000;
+
+            pub ccm<crate::ccm::RegisterBlock> = 0x40CC_0000;
+
+            pub enet<crate::enet::RegisterBlock> = 0x4042_4000;
+            pub enet_1g<crate::enet::RegisterBlock> = 0x4042_0000;
+
+            pub flexspi1<crate::flexspi::RegisterBlock> = 0x400C_C000;
+            pub flexspi2<crate::flexspi::RegisterBlock> = 0x400D_0000;
+
+            pub iomuxc<crate::iomuxc::RegisterBlock> = 0x400E_8000;
+            pub iomuxc_gpr<crate::iomuxc_gpr::RegisterBlock> = 0x400E_4000;
+            pub iomuxc_lpsr<crate::iomuxc_lpsr::RegisterBlock> = 0x40C0_8000;
+
+            pub pit1<crate::pit::RegisterBlock> = 0x400d_8000;
+            pub pit2<crate::pit::RegisterBlock> = 0x40cb_0000;
+
+            pub lpspi1<crate::lpspi::RegisterBlock> = 0x4011_4000;
+            pub lpspi2<crate::lpspi::RegisterBlock> = 0x4011_8000;
+            pub lpspi3<crate::lpspi::RegisterBlock> = 0x4011_c000;
+            pub lpspi4<crate::lpspi::RegisterBlock> = 0x4012_0000;
+            pub lpspi5<crate::lpspi::RegisterBlock> = 0x40c2_c000;
+            pub lpspi6<crate::lpspi::RegisterBlock> = 0x40c3_0000;
+
+            pub gpc_cpu_mode_ctrl0<crate::gpc_cpu_mode_ctrl::RegisterBlock> = 0x40C0_0000;
+            pub gpc_cpu_mode_ctrl1<crate::gpc_cpu_mode_ctrl::RegisterBlock> = 0x40C0_0800;
+
+            pub pmu<crate::pmu::RegisterBlock> = 0x40C8_4000;
+            pub pll<crate::ccm::pll::RegisterBlock> = 0x40C8_4000;
+
+            pub wdog3<crate::rtwdog::RegisterBlock> = 0x4003_8000;
+            pub wdog4<crate::rtwdog::RegisterBlock> = 0x40C1_0000;
+        }
+    }
+}
diff --git a/chips/imxrt1170/src/rt.rs b/chips/imxrt1170/src/rt.rs
new file mode 100644
index 0000000..e0f0dd4
--- /dev/null
+++ b/chips/imxrt1170/src/rt.rs
@@ -0,0 +1,1003 @@
+#![allow(non_camel_case_types)]
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - DMA0_DMA16"]
+    DMA0_DMA16 = 0,
+    #[doc = "1 - DMA1_DMA17"]
+    DMA1_DMA17 = 1,
+    #[doc = "2 - DMA2_DMA18"]
+    DMA2_DMA18 = 2,
+    #[doc = "3 - DMA3_DMA19"]
+    DMA3_DMA19 = 3,
+    #[doc = "4 - DMA4_DMA20"]
+    DMA4_DMA20 = 4,
+    #[doc = "5 - DMA5_DMA21"]
+    DMA5_DMA21 = 5,
+    #[doc = "6 - DMA6_DMA22"]
+    DMA6_DMA22 = 6,
+    #[doc = "7 - DMA7_DMA23"]
+    DMA7_DMA23 = 7,
+    #[doc = "8 - DMA8_DMA24"]
+    DMA8_DMA24 = 8,
+    #[doc = "9 - DMA9_DMA25"]
+    DMA9_DMA25 = 9,
+    #[doc = "10 - DMA10_DMA26"]
+    DMA10_DMA26 = 10,
+    #[doc = "11 - DMA11_DMA27"]
+    DMA11_DMA27 = 11,
+    #[doc = "12 - DMA12_DMA28"]
+    DMA12_DMA28 = 12,
+    #[doc = "13 - DMA13_DMA29"]
+    DMA13_DMA29 = 13,
+    #[doc = "14 - DMA14_DMA30"]
+    DMA14_DMA30 = 14,
+    #[doc = "15 - DMA15_DMA31"]
+    DMA15_DMA31 = 15,
+    #[doc = "16 - DMA_ERROR"]
+    DMA_ERROR = 16,
+    #[doc = "17 - CTI_TRIGGER_OUT0"]
+    CTI_TRIGGER_OUT0 = 17,
+    #[doc = "18 - CTI_TRIGGER_OUT1"]
+    CTI_TRIGGER_OUT1 = 18,
+    #[doc = "19 - CORE"]
+    CORE = 19,
+    #[doc = "20 - LPUART1"]
+    LPUART1 = 20,
+    #[doc = "21 - LPUART2"]
+    LPUART2 = 21,
+    #[doc = "22 - LPUART3"]
+    LPUART3 = 22,
+    #[doc = "23 - LPUART4"]
+    LPUART4 = 23,
+    #[doc = "24 - LPUART5"]
+    LPUART5 = 24,
+    #[doc = "25 - LPUART6"]
+    LPUART6 = 25,
+    #[doc = "26 - LPUART7"]
+    LPUART7 = 26,
+    #[doc = "27 - LPUART8"]
+    LPUART8 = 27,
+    #[doc = "28 - LPUART9"]
+    LPUART9 = 28,
+    #[doc = "29 - LPUART10"]
+    LPUART10 = 29,
+    #[doc = "30 - LPUART11"]
+    LPUART11 = 30,
+    #[doc = "31 - LPUART12"]
+    LPUART12 = 31,
+    #[doc = "32 - LPI2C1"]
+    LPI2C1 = 32,
+    #[doc = "33 - LPI2C2"]
+    LPI2C2 = 33,
+    #[doc = "34 - LPI2C3"]
+    LPI2C3 = 34,
+    #[doc = "35 - LPI2C4"]
+    LPI2C4 = 35,
+    #[doc = "36 - LPI2C5"]
+    LPI2C5 = 36,
+    #[doc = "37 - LPI2C6"]
+    LPI2C6 = 37,
+    #[doc = "38 - LPSPI1"]
+    LPSPI1 = 38,
+    #[doc = "39 - LPSPI2"]
+    LPSPI2 = 39,
+    #[doc = "40 - LPSPI3"]
+    LPSPI3 = 40,
+    #[doc = "41 - LPSPI4"]
+    LPSPI4 = 41,
+    #[doc = "42 - LPSPI5"]
+    LPSPI5 = 42,
+    #[doc = "43 - LPSPI6"]
+    LPSPI6 = 43,
+    #[doc = "44 - CAN1"]
+    CAN1 = 44,
+    #[doc = "45 - CAN1_ERROR"]
+    CAN1_ERROR = 45,
+    #[doc = "46 - CAN2"]
+    CAN2 = 46,
+    #[doc = "47 - CAN2_ERROR"]
+    CAN2_ERROR = 47,
+    #[doc = "48 - CAN3"]
+    CAN3 = 48,
+    #[doc = "49 - CAN3_ERROR"]
+    CAN3_ERROR = 49,
+    #[doc = "50 - FLEXRAM"]
+    FLEXRAM = 50,
+    #[doc = "51 - KPP"]
+    KPP = 51,
+    #[doc = "53 - GPR_IRQ"]
+    GPR_IRQ = 53,
+    #[doc = "54 - ELCDIF"]
+    ELCDIF = 54,
+    #[doc = "55 - LCDIFV2"]
+    LCDIFV2 = 55,
+    #[doc = "56 - CSI"]
+    CSI = 56,
+    #[doc = "57 - PXP"]
+    PXP = 57,
+    #[doc = "58 - MIPI_CSI"]
+    MIPI_CSI = 58,
+    #[doc = "59 - MIPI_DSI"]
+    MIPI_DSI = 59,
+    #[doc = "61 - GPIO6_COMBINED_0_15"]
+    GPIO6_COMBINED_0_15 = 61,
+    #[doc = "62 - GPIO6_COMBINED_16_31"]
+    GPIO6_COMBINED_16_31 = 62,
+    #[doc = "63 - DAC"]
+    DAC = 63,
+    #[doc = "64 - KEY_MANAGER"]
+    KEY_MANAGER = 64,
+    #[doc = "65 - WDOG2"]
+    WDOG2 = 65,
+    #[doc = "66 - SNVS_HP_NON_TZ"]
+    SNVS_HP_NON_TZ = 66,
+    #[doc = "67 - SNVS_HP_TZ"]
+    SNVS_HP_TZ = 67,
+    #[doc = "68 - SNVS_PULSE_EVENT"]
+    SNVS_PULSE_EVENT = 68,
+    #[doc = "69 - CAAM_IRQ0"]
+    CAAM_IRQ0 = 69,
+    #[doc = "70 - CAAM_IRQ1"]
+    CAAM_IRQ1 = 70,
+    #[doc = "71 - CAAM_IRQ2"]
+    CAAM_IRQ2 = 71,
+    #[doc = "72 - CAAM_IRQ3"]
+    CAAM_IRQ3 = 72,
+    #[doc = "73 - CAAM_RECORVE_ERRPR"]
+    CAAM_RECORVE_ERRPR = 73,
+    #[doc = "74 - CAAM_RTIC"]
+    CAAM_RTIC = 74,
+    #[doc = "75 - CDOG"]
+    CDOG = 75,
+    #[doc = "76 - SAI1"]
+    SAI1 = 76,
+    #[doc = "77 - SAI2"]
+    SAI2 = 77,
+    #[doc = "78 - SAI3_RX"]
+    SAI3_RX = 78,
+    #[doc = "79 - SAI3_TX"]
+    SAI3_TX = 79,
+    #[doc = "80 - SAI4_RX"]
+    SAI4_RX = 80,
+    #[doc = "81 - SAI4_TX"]
+    SAI4_TX = 81,
+    #[doc = "82 - SPDIF"]
+    SPDIF = 82,
+    #[doc = "83 - TMPSNS_INT"]
+    TMPSNS_INT = 83,
+    #[doc = "84 - TMPSNS_LOW_HIGH"]
+    TMPSNS_LOW_HIGH = 84,
+    #[doc = "85 - TMPSNS_PANIC"]
+    TMPSNS_PANIC = 85,
+    #[doc = "86 - LPSR_LP8_BROWNOUT"]
+    LPSR_LP8_BROWNOUT = 86,
+    #[doc = "87 - LPSR_LP0_BROWNOUT"]
+    LPSR_LP0_BROWNOUT = 87,
+    #[doc = "88 - ADC1"]
+    ADC1 = 88,
+    #[doc = "89 - ADC2"]
+    ADC2 = 89,
+    #[doc = "90 - USBPHY1"]
+    USBPHY1 = 90,
+    #[doc = "91 - USBPHY2"]
+    USBPHY2 = 91,
+    #[doc = "92 - RDC"]
+    RDC = 92,
+    #[doc = "93 - GPIO13_COMBINED_0_31"]
+    GPIO13_COMBINED_0_31 = 93,
+    #[doc = "95 - DCIC1"]
+    DCIC1 = 95,
+    #[doc = "96 - DCIC2"]
+    DCIC2 = 96,
+    #[doc = "97 - ASRC"]
+    ASRC = 97,
+    #[doc = "98 - FLEXRAM_ECC"]
+    FLEXRAM_ECC = 98,
+    #[doc = "99 - CM7_GPIO2_3"]
+    CM7_GPIO2_3 = 99,
+    #[doc = "100 - GPIO1_COMBINED_0_15"]
+    GPIO1_COMBINED_0_15 = 100,
+    #[doc = "101 - GPIO1_COMBINED_16_31"]
+    GPIO1_COMBINED_16_31 = 101,
+    #[doc = "102 - GPIO2_COMBINED_0_15"]
+    GPIO2_COMBINED_0_15 = 102,
+    #[doc = "103 - GPIO2_COMBINED_16_31"]
+    GPIO2_COMBINED_16_31 = 103,
+    #[doc = "104 - GPIO3_COMBINED_0_15"]
+    GPIO3_COMBINED_0_15 = 104,
+    #[doc = "105 - GPIO3_COMBINED_16_31"]
+    GPIO3_COMBINED_16_31 = 105,
+    #[doc = "106 - GPIO4_COMBINED_0_15"]
+    GPIO4_COMBINED_0_15 = 106,
+    #[doc = "107 - GPIO4_COMBINED_16_31"]
+    GPIO4_COMBINED_16_31 = 107,
+    #[doc = "108 - GPIO5_COMBINED_0_15"]
+    GPIO5_COMBINED_0_15 = 108,
+    #[doc = "109 - GPIO5_COMBINED_16_31"]
+    GPIO5_COMBINED_16_31 = 109,
+    #[doc = "110 - FLEXIO1"]
+    FLEXIO1 = 110,
+    #[doc = "111 - FLEXIO2"]
+    FLEXIO2 = 111,
+    #[doc = "112 - WDOG1"]
+    WDOG1 = 112,
+    #[doc = "113 - RTWDOG3"]
+    RTWDOG3 = 113,
+    #[doc = "114 - EWM"]
+    EWM = 114,
+    #[doc = "115 - OCOTP_READ_FUSE_ERROR"]
+    OCOTP_READ_FUSE_ERROR = 115,
+    #[doc = "116 - OCOTP_READ_DONE_ERROR"]
+    OCOTP_READ_DONE_ERROR = 116,
+    #[doc = "117 - GPC"]
+    GPC = 117,
+    #[doc = "118 - MUA"]
+    MUA = 118,
+    #[doc = "119 - GPT1"]
+    GPT1 = 119,
+    #[doc = "120 - GPT2"]
+    GPT2 = 120,
+    #[doc = "121 - GPT3"]
+    GPT3 = 121,
+    #[doc = "122 - GPT4"]
+    GPT4 = 122,
+    #[doc = "123 - GPT5"]
+    GPT5 = 123,
+    #[doc = "124 - GPT6"]
+    GPT6 = 124,
+    #[doc = "125 - PWM1_0"]
+    PWM1_0 = 125,
+    #[doc = "126 - PWM1_1"]
+    PWM1_1 = 126,
+    #[doc = "127 - PWM1_2"]
+    PWM1_2 = 127,
+    #[doc = "128 - PWM1_3"]
+    PWM1_3 = 128,
+    #[doc = "129 - PWM1_FAULT"]
+    PWM1_FAULT = 129,
+    #[doc = "130 - FLEXSPI1"]
+    FLEXSPI1 = 130,
+    #[doc = "131 - FLEXSPI2"]
+    FLEXSPI2 = 131,
+    #[doc = "132 - SEMC"]
+    SEMC = 132,
+    #[doc = "133 - USDHC1"]
+    USDHC1 = 133,
+    #[doc = "134 - USDHC2"]
+    USDHC2 = 134,
+    #[doc = "135 - USB_OTG2"]
+    USB_OTG2 = 135,
+    #[doc = "136 - USB_OTG1"]
+    USB_OTG1 = 136,
+    #[doc = "137 - ENET"]
+    ENET = 137,
+    #[doc = "138 - ENET_1588_TIMER"]
+    ENET_1588_TIMER = 138,
+    #[doc = "139 - ENET_1G_MAC0_TX_RX_1"]
+    ENET_1G_MAC0_TX_RX_1 = 139,
+    #[doc = "140 - ENET_1G_MAC0_TX_RX_2"]
+    ENET_1G_MAC0_TX_RX_2 = 140,
+    #[doc = "141 - ENET_1G"]
+    ENET_1G = 141,
+    #[doc = "142 - ENET_1G_1588_TIMER"]
+    ENET_1G_1588_TIMER = 142,
+    #[doc = "143 - XBAR1_IRQ_0_1"]
+    XBAR1_IRQ_0_1 = 143,
+    #[doc = "144 - XBAR1_IRQ_2_3"]
+    XBAR1_IRQ_2_3 = 144,
+    #[doc = "145 - ADC_ETC_IRQ0"]
+    ADC_ETC_IRQ0 = 145,
+    #[doc = "146 - ADC_ETC_IRQ1"]
+    ADC_ETC_IRQ1 = 146,
+    #[doc = "147 - ADC_ETC_IRQ2"]
+    ADC_ETC_IRQ2 = 147,
+    #[doc = "148 - ADC_ETC_IRQ3"]
+    ADC_ETC_IRQ3 = 148,
+    #[doc = "149 - ADC_ETC_ERROR_IRQ"]
+    ADC_ETC_ERROR_IRQ = 149,
+    #[doc = "155 - PIT1"]
+    PIT1 = 155,
+    #[doc = "156 - PIT2"]
+    PIT2 = 156,
+    #[doc = "157 - ACMP1"]
+    ACMP1 = 157,
+    #[doc = "158 - ACMP2"]
+    ACMP2 = 158,
+    #[doc = "159 - ACMP3"]
+    ACMP3 = 159,
+    #[doc = "160 - ACMP4"]
+    ACMP4 = 160,
+    #[doc = "165 - ENC1"]
+    ENC1 = 165,
+    #[doc = "166 - ENC2"]
+    ENC2 = 166,
+    #[doc = "167 - ENC3"]
+    ENC3 = 167,
+    #[doc = "168 - ENC4"]
+    ENC4 = 168,
+    #[doc = "171 - TMR1"]
+    TMR1 = 171,
+    #[doc = "172 - TMR2"]
+    TMR2 = 172,
+    #[doc = "173 - TMR3"]
+    TMR3 = 173,
+    #[doc = "174 - TMR4"]
+    TMR4 = 174,
+    #[doc = "175 - SEMA4_CP0"]
+    SEMA4_CP0 = 175,
+    #[doc = "176 - SEMA4_CP1"]
+    SEMA4_CP1 = 176,
+    #[doc = "177 - PWM2_0"]
+    PWM2_0 = 177,
+    #[doc = "178 - PWM2_1"]
+    PWM2_1 = 178,
+    #[doc = "179 - PWM2_2"]
+    PWM2_2 = 179,
+    #[doc = "180 - PWM2_3"]
+    PWM2_3 = 180,
+    #[doc = "181 - PWM2_FAULT"]
+    PWM2_FAULT = 181,
+    #[doc = "182 - PWM3_0"]
+    PWM3_0 = 182,
+    #[doc = "183 - PWM3_1"]
+    PWM3_1 = 183,
+    #[doc = "184 - PWM3_2"]
+    PWM3_2 = 184,
+    #[doc = "185 - PWM3_3"]
+    PWM3_3 = 185,
+    #[doc = "186 - PWM3_FAULT"]
+    PWM3_FAULT = 186,
+    #[doc = "187 - PWM4_0"]
+    PWM4_0 = 187,
+    #[doc = "188 - PWM4_1"]
+    PWM4_1 = 188,
+    #[doc = "189 - PWM4_2"]
+    PWM4_2 = 189,
+    #[doc = "190 - PWM4_3"]
+    PWM4_3 = 190,
+    #[doc = "191 - PWM4_FAULT"]
+    PWM4_FAULT = 191,
+    #[doc = "200 - PDM_HWVAD_EVENT"]
+    PDM_HWVAD_EVENT = 200,
+    #[doc = "201 - PDM_HWVAD_ERROR"]
+    PDM_HWVAD_ERROR = 201,
+    #[doc = "202 - PDM_EVENT"]
+    PDM_EVENT = 202,
+    #[doc = "203 - PDM_ERROR"]
+    PDM_ERROR = 203,
+    #[doc = "204 - EMVSIM1"]
+    EMVSIM1 = 204,
+    #[doc = "205 - EMVSIM2"]
+    EMVSIM2 = 205,
+    #[doc = "206 - MECC1_INT"]
+    MECC1_INT = 206,
+    #[doc = "207 - MECC1_FATAL_INT"]
+    MECC1_FATAL_INT = 207,
+    #[doc = "208 - MECC2_INT"]
+    MECC2_INT = 208,
+    #[doc = "209 - MECC2_FATAL_INT"]
+    MECC2_FATAL_INT = 209,
+    #[doc = "210 - XECC_FLEXSPI1_INT"]
+    XECC_FLEXSPI1_INT = 210,
+    #[doc = "211 - XECC_FLEXSPI1_FATAL_INT"]
+    XECC_FLEXSPI1_FATAL_INT = 211,
+    #[doc = "212 - XECC_FLEXSPI2_INT"]
+    XECC_FLEXSPI2_INT = 212,
+    #[doc = "213 - XECC_FLEXSPI2_FATAL_INT"]
+    XECC_FLEXSPI2_FATAL_INT = 213,
+    #[doc = "214 - XECC_SEMC_INT"]
+    XECC_SEMC_INT = 214,
+    #[doc = "215 - XECC_SEMC_FATAL_INT"]
+    XECC_SEMC_FATAL_INT = 215,
+    #[doc = "216 - ENET_QOS"]
+    ENET_QOS = 216,
+    #[doc = "217 - ENET_QOS_PMT"]
+    ENET_QOS_PMT = 217,
+}
+pub type interrupt = Interrupt;
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+
+mod _vectors {
+    unsafe extern "C" {
+        fn DMA0_DMA16();
+        fn DMA1_DMA17();
+        fn DMA2_DMA18();
+        fn DMA3_DMA19();
+        fn DMA4_DMA20();
+        fn DMA5_DMA21();
+        fn DMA6_DMA22();
+        fn DMA7_DMA23();
+        fn DMA8_DMA24();
+        fn DMA9_DMA25();
+        fn DMA10_DMA26();
+        fn DMA11_DMA27();
+        fn DMA12_DMA28();
+        fn DMA13_DMA29();
+        fn DMA14_DMA30();
+        fn DMA15_DMA31();
+        fn DMA_ERROR();
+        fn CTI_TRIGGER_OUT0();
+        fn CTI_TRIGGER_OUT1();
+        fn CORE();
+        fn LPUART1();
+        fn LPUART2();
+        fn LPUART3();
+        fn LPUART4();
+        fn LPUART5();
+        fn LPUART6();
+        fn LPUART7();
+        fn LPUART8();
+        fn LPUART9();
+        fn LPUART10();
+        fn LPUART11();
+        fn LPUART12();
+        fn LPI2C1();
+        fn LPI2C2();
+        fn LPI2C3();
+        fn LPI2C4();
+        fn LPI2C5();
+        fn LPI2C6();
+        fn LPSPI1();
+        fn LPSPI2();
+        fn LPSPI3();
+        fn LPSPI4();
+        fn LPSPI5();
+        fn LPSPI6();
+        fn CAN1();
+        fn CAN1_ERROR();
+        fn CAN2();
+        fn CAN2_ERROR();
+        fn CAN3();
+        fn CAN3_ERROR();
+        fn FLEXRAM();
+        fn KPP();
+        fn GPR_IRQ();
+        fn ELCDIF();
+        fn LCDIFV2();
+        fn CSI();
+        fn PXP();
+        fn MIPI_CSI();
+        fn MIPI_DSI();
+        fn GPIO6_COMBINED_0_15();
+        fn GPIO6_COMBINED_16_31();
+        fn DAC();
+        fn KEY_MANAGER();
+        fn WDOG2();
+        fn SNVS_HP_NON_TZ();
+        fn SNVS_HP_TZ();
+        fn SNVS_PULSE_EVENT();
+        fn CAAM_IRQ0();
+        fn CAAM_IRQ1();
+        fn CAAM_IRQ2();
+        fn CAAM_IRQ3();
+        fn CAAM_RECORVE_ERRPR();
+        fn CAAM_RTIC();
+        fn CDOG();
+        fn SAI1();
+        fn SAI2();
+        fn SAI3_RX();
+        fn SAI3_TX();
+        fn SAI4_RX();
+        fn SAI4_TX();
+        fn SPDIF();
+        fn TMPSNS_INT();
+        fn TMPSNS_LOW_HIGH();
+        fn TMPSNS_PANIC();
+        fn LPSR_LP8_BROWNOUT();
+        fn LPSR_LP0_BROWNOUT();
+        fn ADC1();
+        fn ADC2();
+        fn USBPHY1();
+        fn USBPHY2();
+        fn RDC();
+        fn GPIO13_COMBINED_0_31();
+        fn DCIC1();
+        fn DCIC2();
+        fn ASRC();
+        fn FLEXRAM_ECC();
+        fn CM7_GPIO2_3();
+        fn GPIO1_COMBINED_0_15();
+        fn GPIO1_COMBINED_16_31();
+        fn GPIO2_COMBINED_0_15();
+        fn GPIO2_COMBINED_16_31();
+        fn GPIO3_COMBINED_0_15();
+        fn GPIO3_COMBINED_16_31();
+        fn GPIO4_COMBINED_0_15();
+        fn GPIO4_COMBINED_16_31();
+        fn GPIO5_COMBINED_0_15();
+        fn GPIO5_COMBINED_16_31();
+        fn FLEXIO1();
+        fn FLEXIO2();
+        fn WDOG1();
+        fn RTWDOG3();
+        fn EWM();
+        fn OCOTP_READ_FUSE_ERROR();
+        fn OCOTP_READ_DONE_ERROR();
+        fn GPC();
+        fn MUA();
+        fn GPT1();
+        fn GPT2();
+        fn GPT3();
+        fn GPT4();
+        fn GPT5();
+        fn GPT6();
+        fn PWM1_0();
+        fn PWM1_1();
+        fn PWM1_2();
+        fn PWM1_3();
+        fn PWM1_FAULT();
+        fn FLEXSPI1();
+        fn FLEXSPI2();
+        fn SEMC();
+        fn USDHC1();
+        fn USDHC2();
+        fn USB_OTG2();
+        fn USB_OTG1();
+        fn ENET();
+        fn ENET_1588_TIMER();
+        fn ENET_1G_MAC0_TX_RX_1();
+        fn ENET_1G_MAC0_TX_RX_2();
+        fn ENET_1G();
+        fn ENET_1G_1588_TIMER();
+        fn XBAR1_IRQ_0_1();
+        fn XBAR1_IRQ_2_3();
+        fn ADC_ETC_IRQ0();
+        fn ADC_ETC_IRQ1();
+        fn ADC_ETC_IRQ2();
+        fn ADC_ETC_IRQ3();
+        fn ADC_ETC_ERROR_IRQ();
+        fn PIT1();
+        fn PIT2();
+        fn ACMP1();
+        fn ACMP2();
+        fn ACMP3();
+        fn ACMP4();
+        fn ENC1();
+        fn ENC2();
+        fn ENC3();
+        fn ENC4();
+        fn TMR1();
+        fn TMR2();
+        fn TMR3();
+        fn TMR4();
+        fn SEMA4_CP0();
+        fn SEMA4_CP1();
+        fn PWM2_0();
+        fn PWM2_1();
+        fn PWM2_2();
+        fn PWM2_3();
+        fn PWM2_FAULT();
+        fn PWM3_0();
+        fn PWM3_1();
+        fn PWM3_2();
+        fn PWM3_3();
+        fn PWM3_FAULT();
+        fn PWM4_0();
+        fn PWM4_1();
+        fn PWM4_2();
+        fn PWM4_3();
+        fn PWM4_FAULT();
+        fn PDM_HWVAD_EVENT();
+        fn PDM_HWVAD_ERROR();
+        fn PDM_EVENT();
+        fn PDM_ERROR();
+        fn EMVSIM1();
+        fn EMVSIM2();
+        fn MECC1_INT();
+        fn MECC1_FATAL_INT();
+        fn MECC2_INT();
+        fn MECC2_FATAL_INT();
+        fn XECC_FLEXSPI1_INT();
+        fn XECC_FLEXSPI1_FATAL_INT();
+        fn XECC_FLEXSPI2_INT();
+        fn XECC_FLEXSPI2_FATAL_INT();
+        fn XECC_SEMC_INT();
+        fn XECC_SEMC_FATAL_INT();
+        fn ENET_QOS();
+        fn ENET_QOS_PMT();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".vector_table.interrupts"))]
+    #[unsafe(no_mangle)]
+    pub static __INTERRUPTS: [Vector; 218] = [
+        Vector {
+            _handler: DMA0_DMA16,
+        },
+        Vector {
+            _handler: DMA1_DMA17,
+        },
+        Vector {
+            _handler: DMA2_DMA18,
+        },
+        Vector {
+            _handler: DMA3_DMA19,
+        },
+        Vector {
+            _handler: DMA4_DMA20,
+        },
+        Vector {
+            _handler: DMA5_DMA21,
+        },
+        Vector {
+            _handler: DMA6_DMA22,
+        },
+        Vector {
+            _handler: DMA7_DMA23,
+        },
+        Vector {
+            _handler: DMA8_DMA24,
+        },
+        Vector {
+            _handler: DMA9_DMA25,
+        },
+        Vector {
+            _handler: DMA10_DMA26,
+        },
+        Vector {
+            _handler: DMA11_DMA27,
+        },
+        Vector {
+            _handler: DMA12_DMA28,
+        },
+        Vector {
+            _handler: DMA13_DMA29,
+        },
+        Vector {
+            _handler: DMA14_DMA30,
+        },
+        Vector {
+            _handler: DMA15_DMA31,
+        },
+        Vector {
+            _handler: DMA_ERROR,
+        },
+        Vector {
+            _handler: CTI_TRIGGER_OUT0,
+        },
+        Vector {
+            _handler: CTI_TRIGGER_OUT1,
+        },
+        Vector { _handler: CORE },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: LPUART2 },
+        Vector { _handler: LPUART3 },
+        Vector { _handler: LPUART4 },
+        Vector { _handler: LPUART5 },
+        Vector { _handler: LPUART6 },
+        Vector { _handler: LPUART7 },
+        Vector { _handler: LPUART8 },
+        Vector { _handler: LPUART9 },
+        Vector { _handler: LPUART10 },
+        Vector { _handler: LPUART11 },
+        Vector { _handler: LPUART12 },
+        Vector { _handler: LPI2C1 },
+        Vector { _handler: LPI2C2 },
+        Vector { _handler: LPI2C3 },
+        Vector { _handler: LPI2C4 },
+        Vector { _handler: LPI2C5 },
+        Vector { _handler: LPI2C6 },
+        Vector { _handler: LPSPI1 },
+        Vector { _handler: LPSPI2 },
+        Vector { _handler: LPSPI3 },
+        Vector { _handler: LPSPI4 },
+        Vector { _handler: LPSPI5 },
+        Vector { _handler: LPSPI6 },
+        Vector { _handler: CAN1 },
+        Vector {
+            _handler: CAN1_ERROR,
+        },
+        Vector { _handler: CAN2 },
+        Vector {
+            _handler: CAN2_ERROR,
+        },
+        Vector { _handler: CAN3 },
+        Vector {
+            _handler: CAN3_ERROR,
+        },
+        Vector { _handler: FLEXRAM },
+        Vector { _handler: KPP },
+        Vector { _reserved: 0 },
+        Vector { _handler: GPR_IRQ },
+        Vector { _handler: ELCDIF },
+        Vector { _handler: LCDIFV2 },
+        Vector { _handler: CSI },
+        Vector { _handler: PXP },
+        Vector { _handler: MIPI_CSI },
+        Vector { _handler: MIPI_DSI },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: GPIO6_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO6_COMBINED_16_31,
+        },
+        Vector { _handler: DAC },
+        Vector {
+            _handler: KEY_MANAGER,
+        },
+        Vector { _handler: WDOG2 },
+        Vector {
+            _handler: SNVS_HP_NON_TZ,
+        },
+        Vector {
+            _handler: SNVS_HP_TZ,
+        },
+        Vector {
+            _handler: SNVS_PULSE_EVENT,
+        },
+        Vector {
+            _handler: CAAM_IRQ0,
+        },
+        Vector {
+            _handler: CAAM_IRQ1,
+        },
+        Vector {
+            _handler: CAAM_IRQ2,
+        },
+        Vector {
+            _handler: CAAM_IRQ3,
+        },
+        Vector {
+            _handler: CAAM_RECORVE_ERRPR,
+        },
+        Vector {
+            _handler: CAAM_RTIC,
+        },
+        Vector { _handler: CDOG },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SAI3_RX },
+        Vector { _handler: SAI3_TX },
+        Vector { _handler: SAI4_RX },
+        Vector { _handler: SAI4_TX },
+        Vector { _handler: SPDIF },
+        Vector {
+            _handler: TMPSNS_INT,
+        },
+        Vector {
+            _handler: TMPSNS_LOW_HIGH,
+        },
+        Vector {
+            _handler: TMPSNS_PANIC,
+        },
+        Vector {
+            _handler: LPSR_LP8_BROWNOUT,
+        },
+        Vector {
+            _handler: LPSR_LP0_BROWNOUT,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: ADC2 },
+        Vector { _handler: USBPHY1 },
+        Vector { _handler: USBPHY2 },
+        Vector { _handler: RDC },
+        Vector {
+            _handler: GPIO13_COMBINED_0_31,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: DCIC1 },
+        Vector { _handler: DCIC2 },
+        Vector { _handler: ASRC },
+        Vector {
+            _handler: FLEXRAM_ECC,
+        },
+        Vector {
+            _handler: CM7_GPIO2_3,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO1_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO2_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO3_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO4_COMBINED_16_31,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_0_15,
+        },
+        Vector {
+            _handler: GPIO5_COMBINED_16_31,
+        },
+        Vector { _handler: FLEXIO1 },
+        Vector { _handler: FLEXIO2 },
+        Vector { _handler: WDOG1 },
+        Vector { _handler: RTWDOG3 },
+        Vector { _handler: EWM },
+        Vector {
+            _handler: OCOTP_READ_FUSE_ERROR,
+        },
+        Vector {
+            _handler: OCOTP_READ_DONE_ERROR,
+        },
+        Vector { _handler: GPC },
+        Vector { _handler: MUA },
+        Vector { _handler: GPT1 },
+        Vector { _handler: GPT2 },
+        Vector { _handler: GPT3 },
+        Vector { _handler: GPT4 },
+        Vector { _handler: GPT5 },
+        Vector { _handler: GPT6 },
+        Vector { _handler: PWM1_0 },
+        Vector { _handler: PWM1_1 },
+        Vector { _handler: PWM1_2 },
+        Vector { _handler: PWM1_3 },
+        Vector {
+            _handler: PWM1_FAULT,
+        },
+        Vector { _handler: FLEXSPI1 },
+        Vector { _handler: FLEXSPI2 },
+        Vector { _handler: SEMC },
+        Vector { _handler: USDHC1 },
+        Vector { _handler: USDHC2 },
+        Vector { _handler: USB_OTG2 },
+        Vector { _handler: USB_OTG1 },
+        Vector { _handler: ENET },
+        Vector {
+            _handler: ENET_1588_TIMER,
+        },
+        Vector {
+            _handler: ENET_1G_MAC0_TX_RX_1,
+        },
+        Vector {
+            _handler: ENET_1G_MAC0_TX_RX_2,
+        },
+        Vector { _handler: ENET_1G },
+        Vector {
+            _handler: ENET_1G_1588_TIMER,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_0_1,
+        },
+        Vector {
+            _handler: XBAR1_IRQ_2_3,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ0,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ1,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ2,
+        },
+        Vector {
+            _handler: ADC_ETC_IRQ3,
+        },
+        Vector {
+            _handler: ADC_ETC_ERROR_IRQ,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: PIT1 },
+        Vector { _handler: PIT2 },
+        Vector { _handler: ACMP1 },
+        Vector { _handler: ACMP2 },
+        Vector { _handler: ACMP3 },
+        Vector { _handler: ACMP4 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: ENC1 },
+        Vector { _handler: ENC2 },
+        Vector { _handler: ENC3 },
+        Vector { _handler: ENC4 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TMR1 },
+        Vector { _handler: TMR2 },
+        Vector { _handler: TMR3 },
+        Vector { _handler: TMR4 },
+        Vector {
+            _handler: SEMA4_CP0,
+        },
+        Vector {
+            _handler: SEMA4_CP1,
+        },
+        Vector { _handler: PWM2_0 },
+        Vector { _handler: PWM2_1 },
+        Vector { _handler: PWM2_2 },
+        Vector { _handler: PWM2_3 },
+        Vector {
+            _handler: PWM2_FAULT,
+        },
+        Vector { _handler: PWM3_0 },
+        Vector { _handler: PWM3_1 },
+        Vector { _handler: PWM3_2 },
+        Vector { _handler: PWM3_3 },
+        Vector {
+            _handler: PWM3_FAULT,
+        },
+        Vector { _handler: PWM4_0 },
+        Vector { _handler: PWM4_1 },
+        Vector { _handler: PWM4_2 },
+        Vector { _handler: PWM4_3 },
+        Vector {
+            _handler: PWM4_FAULT,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: PDM_HWVAD_EVENT,
+        },
+        Vector {
+            _handler: PDM_HWVAD_ERROR,
+        },
+        Vector {
+            _handler: PDM_EVENT,
+        },
+        Vector {
+            _handler: PDM_ERROR,
+        },
+        Vector { _handler: EMVSIM1 },
+        Vector { _handler: EMVSIM2 },
+        Vector {
+            _handler: MECC1_INT,
+        },
+        Vector {
+            _handler: MECC1_FATAL_INT,
+        },
+        Vector {
+            _handler: MECC2_INT,
+        },
+        Vector {
+            _handler: MECC2_FATAL_INT,
+        },
+        Vector {
+            _handler: XECC_FLEXSPI1_INT,
+        },
+        Vector {
+            _handler: XECC_FLEXSPI1_FATAL_INT,
+        },
+        Vector {
+            _handler: XECC_FLEXSPI2_INT,
+        },
+        Vector {
+            _handler: XECC_FLEXSPI2_FATAL_INT,
+        },
+        Vector {
+            _handler: XECC_SEMC_INT,
+        },
+        Vector {
+            _handler: XECC_SEMC_FATAL_INT,
+        },
+        Vector { _handler: ENET_QOS },
+        Vector {
+            _handler: ENET_QOS_PMT,
+        },
+    ];
+}
diff --git a/chips/imxrt1180/Cargo.toml b/chips/imxrt1180/Cargo.toml
new file mode 100644
index 0000000..f01d3ad
--- /dev/null
+++ b/chips/imxrt1180/Cargo.toml
@@ -0,0 +1,13 @@
+[package]
+name = "imxrt1180"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+cortex-m = { workspace = true }
+ral-registers = { workspace = true }
+
+imxrt-drivers-ccm-11xx = { workspace = true }
+imxrt-drivers-iomuxc-11xx = { workspace = true }
+imxrt-drivers-lpspi= { workspace = true }
+imxrt-drivers-rgpio = { workspace = true }
diff --git a/chips/imxrt1180/build.rs b/chips/imxrt1180/build.rs
new file mode 100644
index 0000000..1696d23
--- /dev/null
+++ b/chips/imxrt1180/build.rs
@@ -0,0 +1,8 @@
+use std::{env, fs, path};
+
+fn main() {
+    let out_dir = path::PathBuf::from(env::var("OUT_DIR").unwrap());
+    fs::copy("device.x", out_dir.join("device.x")).unwrap();
+    fs::copy("device.x", out_dir.join("imxrt1180.x")).unwrap();
+    println!("cargo::rustc-link-search={}", out_dir.display());
+}
diff --git a/chips/imxrt1180/device.x b/chips/imxrt1180/device.x
new file mode 100644
index 0000000..dd4dcad
--- /dev/null
+++ b/chips/imxrt1180/device.x
@@ -0,0 +1,188 @@
+PROVIDE(TMR1 = DefaultHandler);
+PROVIDE(TMR5 = DefaultHandler);
+PROVIDE(TMR6 = DefaultHandler);
+PROVIDE(TMR7 = DefaultHandler);
+PROVIDE(TMR8 = DefaultHandler);
+PROVIDE(CAN1 = DefaultHandler);
+PROVIDE(CAN1_ERROR = DefaultHandler);
+PROVIDE(GPIO1_0 = DefaultHandler);
+PROVIDE(GPIO1_1 = DefaultHandler);
+PROVIDE(I3C1 = DefaultHandler);
+PROVIDE(LPI2C1 = DefaultHandler);
+PROVIDE(LPI2C2 = DefaultHandler);
+PROVIDE(LPIT1 = DefaultHandler);
+PROVIDE(LPSPI1 = DefaultHandler);
+PROVIDE(LPSPI2 = DefaultHandler);
+PROVIDE(LPTMR1 = DefaultHandler);
+PROVIDE(LPUART1 = DefaultHandler);
+PROVIDE(LPUART2 = DefaultHandler);
+PROVIDE(MU1 = DefaultHandler);
+PROVIDE(MU2 = DefaultHandler);
+PROVIDE(PWM1_FAULT = DefaultHandler);
+PROVIDE(PWM1_0 = DefaultHandler);
+PROVIDE(PWM1_1 = DefaultHandler);
+PROVIDE(PWM1_2 = DefaultHandler);
+PROVIDE(PWM1_3 = DefaultHandler);
+PROVIDE(TPM1 = DefaultHandler);
+PROVIDE(TPM2 = DefaultHandler);
+PROVIDE(RTWDOG1 = DefaultHandler);
+PROVIDE(RTWDOG2 = DefaultHandler);
+PROVIDE(TRDC_MGR_AON = DefaultHandler);
+PROVIDE(PDM_HWVAD_EVENT = DefaultHandler);
+PROVIDE(PDM_HWVAD_ERROR = DefaultHandler);
+PROVIDE(PDM_EVENT = DefaultHandler);
+PROVIDE(PDM_ERROR = DefaultHandler);
+PROVIDE(SAI1 = DefaultHandler);
+PROVIDE(CAN2 = DefaultHandler);
+PROVIDE(CAN2_ERROR = DefaultHandler);
+PROVIDE(FLEXIO1 = DefaultHandler);
+PROVIDE(FLEXIO2 = DefaultHandler);
+PROVIDE(FLEXSPI1 = DefaultHandler);
+PROVIDE(FLEXSPI2 = DefaultHandler);
+PROVIDE(GPIO2_0 = DefaultHandler);
+PROVIDE(GPIO2_1 = DefaultHandler);
+PROVIDE(GPIO3_0 = DefaultHandler);
+PROVIDE(GPIO3_1 = DefaultHandler);
+PROVIDE(I3C2 = DefaultHandler);
+PROVIDE(LPI2C3 = DefaultHandler);
+PROVIDE(LPI2C4 = DefaultHandler);
+PROVIDE(LPIT2 = DefaultHandler);
+PROVIDE(LPSPI3 = DefaultHandler);
+PROVIDE(LPSPI4 = DefaultHandler);
+PROVIDE(LPTMR2 = DefaultHandler);
+PROVIDE(LPUART3 = DefaultHandler);
+PROVIDE(LPUART4 = DefaultHandler);
+PROVIDE(LPUART5 = DefaultHandler);
+PROVIDE(LPUART6 = DefaultHandler);
+PROVIDE(BBNSM = DefaultHandler);
+PROVIDE(TPM3 = DefaultHandler);
+PROVIDE(TPM4 = DefaultHandler);
+PROVIDE(TPM5 = DefaultHandler);
+PROVIDE(TPM6 = DefaultHandler);
+PROVIDE(RTWDOG3 = DefaultHandler);
+PROVIDE(RTWDOG4 = DefaultHandler);
+PROVIDE(RTWDOG5 = DefaultHandler);
+PROVIDE(TRDC_MGR_WKUP = DefaultHandler);
+PROVIDE(USDHC1 = DefaultHandler);
+PROVIDE(USDHC2 = DefaultHandler);
+PROVIDE(TRDC_MGR_MEGA = DefaultHandler);
+PROVIDE(ADC1 = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(DMA3_CH0 = DefaultHandler);
+PROVIDE(DMA3_CH1 = DefaultHandler);
+PROVIDE(DMA3_CH2 = DefaultHandler);
+PROVIDE(DMA3_CH3 = DefaultHandler);
+PROVIDE(DMA3_CH4 = DefaultHandler);
+PROVIDE(DMA3_CH5 = DefaultHandler);
+PROVIDE(DMA3_CH6 = DefaultHandler);
+PROVIDE(DMA3_CH7 = DefaultHandler);
+PROVIDE(DMA3_CH8 = DefaultHandler);
+PROVIDE(DMA3_CH9 = DefaultHandler);
+PROVIDE(DMA3_CH10 = DefaultHandler);
+PROVIDE(DMA3_CH11 = DefaultHandler);
+PROVIDE(DMA3_CH12 = DefaultHandler);
+PROVIDE(DMA3_CH13 = DefaultHandler);
+PROVIDE(DMA3_CH14 = DefaultHandler);
+PROVIDE(DMA3_CH15 = DefaultHandler);
+PROVIDE(DMA3_CH16 = DefaultHandler);
+PROVIDE(DMA3_CH17 = DefaultHandler);
+PROVIDE(DMA3_CH18 = DefaultHandler);
+PROVIDE(DMA3_CH19 = DefaultHandler);
+PROVIDE(DMA3_CH20 = DefaultHandler);
+PROVIDE(DMA3_CH21 = DefaultHandler);
+PROVIDE(DMA3_CH22 = DefaultHandler);
+PROVIDE(DMA3_CH23 = DefaultHandler);
+PROVIDE(DMA3_CH24 = DefaultHandler);
+PROVIDE(DMA3_CH25 = DefaultHandler);
+PROVIDE(DMA3_CH26 = DefaultHandler);
+PROVIDE(DMA3_CH27 = DefaultHandler);
+PROVIDE(DMA3_CH28 = DefaultHandler);
+PROVIDE(DMA3_CH29 = DefaultHandler);
+PROVIDE(DMA3_CH30 = DefaultHandler);
+PROVIDE(DMA3_CH31 = DefaultHandler);
+PROVIDE(DMA4_ERROR = DefaultHandler);
+PROVIDE(DMA4_CH0_CH1_CH32_CH33 = DefaultHandler);
+PROVIDE(DMA4_CH2_CH3_CH34_CH35 = DefaultHandler);
+PROVIDE(DMA4_CH4_CH5_CH36_CH37 = DefaultHandler);
+PROVIDE(DMA4_CH6_CH7_CH38_CH39 = DefaultHandler);
+PROVIDE(DMA4_CH8_CH9_CH40_CH41 = DefaultHandler);
+PROVIDE(DMA4_CH10_CH11_CH42_CH43 = DefaultHandler);
+PROVIDE(DMA4_CH12_CH13_CH44_CH45 = DefaultHandler);
+PROVIDE(DMA4_CH14_CH15_CH46_CH47 = DefaultHandler);
+PROVIDE(DMA4_CH16_CH17_CH48_CH49 = DefaultHandler);
+PROVIDE(DMA4_CH18_CH19_CH50_CH51 = DefaultHandler);
+PROVIDE(DMA4_CH20_CH21_CH52_CH53 = DefaultHandler);
+PROVIDE(DMA4_CH22_CH23_CH54_CH55 = DefaultHandler);
+PROVIDE(DMA4_CH24_CH25_CH56_CH57 = DefaultHandler);
+PROVIDE(DMA4_CH26_CH27_CH58_CH59 = DefaultHandler);
+PROVIDE(DMA4_CH28_CH29_CH60_CH61 = DefaultHandler);
+PROVIDE(DMA4_CH30_CH31_CH62_CH63 = DefaultHandler);
+PROVIDE(SINC3_CH0_CH1_CH2_CH3 = DefaultHandler);
+PROVIDE(EWM = DefaultHandler);
+PROVIDE(SEMC = DefaultHandler);
+PROVIDE(LPIT3 = DefaultHandler);
+PROVIDE(LPTMR3 = DefaultHandler);
+PROVIDE(TMR4 = DefaultHandler);
+PROVIDE(LPI2C5 = DefaultHandler);
+PROVIDE(LPI2C6 = DefaultHandler);
+PROVIDE(SAI4 = DefaultHandler);
+PROVIDE(SPDIF = DefaultHandler);
+PROVIDE(LPUART9 = DefaultHandler);
+PROVIDE(LPUART10 = DefaultHandler);
+PROVIDE(LPUART11 = DefaultHandler);
+PROVIDE(LPUART12 = DefaultHandler);
+PROVIDE(TMR3 = DefaultHandler);
+PROVIDE(PWM2_FAULT = DefaultHandler);
+PROVIDE(PWM2_0 = DefaultHandler);
+PROVIDE(PWM2_1 = DefaultHandler);
+PROVIDE(PWM2_2 = DefaultHandler);
+PROVIDE(PWM2_3 = DefaultHandler);
+PROVIDE(PWM3_FAULT = DefaultHandler);
+PROVIDE(PWM3_0 = DefaultHandler);
+PROVIDE(PWM3_1 = DefaultHandler);
+PROVIDE(PWM3_2 = DefaultHandler);
+PROVIDE(PWM3_3 = DefaultHandler);
+PROVIDE(PWM4_FAULT = DefaultHandler);
+PROVIDE(PWM4_0 = DefaultHandler);
+PROVIDE(PWM4_1 = DefaultHandler);
+PROVIDE(PWM4_2 = DefaultHandler);
+PROVIDE(PWM4_3 = DefaultHandler);
+PROVIDE(EQDC1 = DefaultHandler);
+PROVIDE(EQDC2 = DefaultHandler);
+PROVIDE(EQDC3 = DefaultHandler);
+PROVIDE(EQDC4 = DefaultHandler);
+PROVIDE(ADC2 = DefaultHandler);
+PROVIDE(DCDC = DefaultHandler);
+PROVIDE(CAN3 = DefaultHandler);
+PROVIDE(CAN3_ERROR = DefaultHandler);
+PROVIDE(DAC = DefaultHandler);
+PROVIDE(LPSPI5 = DefaultHandler);
+PROVIDE(LPSPI6 = DefaultHandler);
+PROVIDE(LPUART7 = DefaultHandler);
+PROVIDE(LPUART8 = DefaultHandler);
+PROVIDE(SAI2 = DefaultHandler);
+PROVIDE(SAI3 = DefaultHandler);
+PROVIDE(ACMP1 = DefaultHandler);
+PROVIDE(ACMP2 = DefaultHandler);
+PROVIDE(ACMP3 = DefaultHandler);
+PROVIDE(ACMP4 = DefaultHandler);
+PROVIDE(GPT1 = DefaultHandler);
+PROVIDE(GPT2 = DefaultHandler);
+PROVIDE(KPP = DefaultHandler);
+PROVIDE(USBPHY1 = DefaultHandler);
+PROVIDE(USBPHY2 = DefaultHandler);
+PROVIDE(USB_OTG2 = DefaultHandler);
+PROVIDE(USB_OTG1 = DefaultHandler);
+PROVIDE(SINC1_CH0 = DefaultHandler);
+PROVIDE(SINC1_CH1 = DefaultHandler);
+PROVIDE(SINC1_CH2 = DefaultHandler);
+PROVIDE(SINC1_CH3 = DefaultHandler);
+PROVIDE(SINC2_CH0 = DefaultHandler);
+PROVIDE(SINC2_CH1 = DefaultHandler);
+PROVIDE(SINC2_CH2 = DefaultHandler);
+PROVIDE(SINC2_CH3 = DefaultHandler);
+PROVIDE(GPIO4 = DefaultHandler);
+PROVIDE(TMR2 = DefaultHandler);
+PROVIDE(GPIO5 = DefaultHandler);
+PROVIDE(ASRC = DefaultHandler);
+PROVIDE(GPIO6 = DefaultHandler);
diff --git a/chips/imxrt1180/src/lib.rs b/chips/imxrt1180/src/lib.rs
new file mode 100644
index 0000000..7e70e33
--- /dev/null
+++ b/chips/imxrt1180/src/lib.rs
@@ -0,0 +1,33 @@
+#![no_std]
+
+mod rt;
+pub use rt::*;
+
+pub use imxrt_drivers_ccm_11xx::ral_1180 as ccm;
+pub use imxrt_drivers_iomuxc_11xx::iomuxc_aon;
+pub use imxrt_drivers_lpspi as lpspi;
+pub use imxrt_drivers_rgpio as rgpio;
+
+pub mod instances {
+    ral_registers::instances! {
+        unsafe {
+            pub ccm<crate::ccm::RegisterBlock> = 0x4445_0000;
+
+            pub rgpio1<crate::rgpio::RegisterBlock> = 0x4740_0000;
+            pub rgpio2<crate::rgpio::RegisterBlock> = 0x4381_0000;
+            pub rgpio3<crate::rgpio::RegisterBlock> = 0x4382_0000;
+            pub rgpio4<crate::rgpio::RegisterBlock> = 0x4383_0000;
+            pub rgpio5<crate::rgpio::RegisterBlock> = 0x4384_0000;
+            pub rgpio6<crate::rgpio::RegisterBlock> = 0x4385_0000;
+
+            pub iomuxc_aon<crate::iomuxc_aon::RegisterBlock> = 0x443C_0000;
+
+            pub lpspi1<crate::lpspi::RegisterBlock> = 0x4436_0000;
+            pub lpspi2<crate::lpspi::RegisterBlock> = 0x4437_0000;
+            pub lpspi3<crate::lpspi::RegisterBlock> = 0x4255_0000;
+            pub lpspi4<crate::lpspi::RegisterBlock> = 0x4256_0000;
+            pub lpspi5<crate::lpspi::RegisterBlock> = 0x42d5_0000;
+            pub lpspi6<crate::lpspi::RegisterBlock> = 0x42d6_0000;
+        }
+    }
+}
diff --git a/chips/imxrt1180/src/rt.rs b/chips/imxrt1180/src/rt.rs
new file mode 100644
index 0000000..a6b3663
--- /dev/null
+++ b/chips/imxrt1180/src/rt.rs
@@ -0,0 +1,952 @@
+#![allow(non_camel_case_types)]
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+    #[doc = "0 - TMR1"]
+    TMR1 = 0,
+    #[doc = "4 - TMR5"]
+    TMR5 = 4,
+    #[doc = "5 - TMR6"]
+    TMR6 = 5,
+    #[doc = "6 - TMR7"]
+    TMR7 = 6,
+    #[doc = "7 - TMR8"]
+    TMR8 = 7,
+    #[doc = "8 - CAN1"]
+    CAN1 = 8,
+    #[doc = "9 - CAN1_ERROR"]
+    CAN1_ERROR = 9,
+    #[doc = "10 - GPIO1_0"]
+    GPIO1_0 = 10,
+    #[doc = "11 - GPIO1_1"]
+    GPIO1_1 = 11,
+    #[doc = "12 - I3C1"]
+    I3C1 = 12,
+    #[doc = "13 - LPI2C1"]
+    LPI2C1 = 13,
+    #[doc = "14 - LPI2C2"]
+    LPI2C2 = 14,
+    #[doc = "15 - LPIT1"]
+    LPIT1 = 15,
+    #[doc = "16 - LPSPI1"]
+    LPSPI1 = 16,
+    #[doc = "17 - LPSPI2"]
+    LPSPI2 = 17,
+    #[doc = "18 - LPTMR1"]
+    LPTMR1 = 18,
+    #[doc = "19 - LPUART1"]
+    LPUART1 = 19,
+    #[doc = "20 - LPUART2"]
+    LPUART2 = 20,
+    #[doc = "21 - MU1"]
+    MU1 = 21,
+    #[doc = "22 - MU2"]
+    MU2 = 22,
+    #[doc = "23 - PWM1_FAULT"]
+    PWM1_FAULT = 23,
+    #[doc = "24 - PWM1_0"]
+    PWM1_0 = 24,
+    #[doc = "25 - PWM1_1"]
+    PWM1_1 = 25,
+    #[doc = "26 - PWM1_2"]
+    PWM1_2 = 26,
+    #[doc = "27 - PWM1_3"]
+    PWM1_3 = 27,
+    #[doc = "36 - TPM1"]
+    TPM1 = 36,
+    #[doc = "37 - TPM2"]
+    TPM2 = 37,
+    #[doc = "38 - RTWDOG1"]
+    RTWDOG1 = 38,
+    #[doc = "39 - RTWDOG2"]
+    RTWDOG2 = 39,
+    #[doc = "40 - TRDC_MGR_AON"]
+    TRDC_MGR_AON = 40,
+    #[doc = "41 - PDM_HWVAD_EVENT"]
+    PDM_HWVAD_EVENT = 41,
+    #[doc = "42 - PDM_HWVAD_ERROR"]
+    PDM_HWVAD_ERROR = 42,
+    #[doc = "43 - PDM_EVENT"]
+    PDM_EVENT = 43,
+    #[doc = "44 - PDM_ERROR"]
+    PDM_ERROR = 44,
+    #[doc = "45 - SAI1"]
+    SAI1 = 45,
+    #[doc = "51 - CAN2"]
+    CAN2 = 51,
+    #[doc = "52 - CAN2_ERROR"]
+    CAN2_ERROR = 52,
+    #[doc = "53 - FLEXIO1"]
+    FLEXIO1 = 53,
+    #[doc = "54 - FLEXIO2"]
+    FLEXIO2 = 54,
+    #[doc = "55 - FLEXSPI1"]
+    FLEXSPI1 = 55,
+    #[doc = "56 - FLEXSPI2"]
+    FLEXSPI2 = 56,
+    #[doc = "57 - GPIO2_0"]
+    GPIO2_0 = 57,
+    #[doc = "58 - GPIO2_1"]
+    GPIO2_1 = 58,
+    #[doc = "59 - GPIO3_0"]
+    GPIO3_0 = 59,
+    #[doc = "60 - GPIO3_1"]
+    GPIO3_1 = 60,
+    #[doc = "61 - I3C2"]
+    I3C2 = 61,
+    #[doc = "62 - LPI2C3"]
+    LPI2C3 = 62,
+    #[doc = "63 - LPI2C4"]
+    LPI2C4 = 63,
+    #[doc = "64 - LPIT2"]
+    LPIT2 = 64,
+    #[doc = "65 - LPSPI3"]
+    LPSPI3 = 65,
+    #[doc = "66 - LPSPI4"]
+    LPSPI4 = 66,
+    #[doc = "67 - LPTMR2"]
+    LPTMR2 = 67,
+    #[doc = "68 - LPUART3"]
+    LPUART3 = 68,
+    #[doc = "69 - LPUART4"]
+    LPUART4 = 69,
+    #[doc = "70 - LPUART5"]
+    LPUART5 = 70,
+    #[doc = "71 - LPUART6"]
+    LPUART6 = 71,
+    #[doc = "73 - BBNSM"]
+    BBNSM = 73,
+    #[doc = "75 - TPM3"]
+    TPM3 = 75,
+    #[doc = "76 - TPM4"]
+    TPM4 = 76,
+    #[doc = "77 - TPM5"]
+    TPM5 = 77,
+    #[doc = "78 - TPM6"]
+    TPM6 = 78,
+    #[doc = "79 - RTWDOG3"]
+    RTWDOG3 = 79,
+    #[doc = "80 - RTWDOG4"]
+    RTWDOG4 = 80,
+    #[doc = "81 - RTWDOG5"]
+    RTWDOG5 = 81,
+    #[doc = "82 - TRDC_MGR_WKUP"]
+    TRDC_MGR_WKUP = 82,
+    #[doc = "86 - USDHC1"]
+    USDHC1 = 86,
+    #[doc = "87 - USDHC2"]
+    USDHC2 = 87,
+    #[doc = "88 - TRDC_MGR_MEGA"]
+    TRDC_MGR_MEGA = 88,
+    #[doc = "93 - ADC1"]
+    ADC1 = 93,
+    #[doc = "94 - DMA_ERROR"]
+    DMA_ERROR = 94,
+    #[doc = "95 - DMA3_CH0"]
+    DMA3_CH0 = 95,
+    #[doc = "96 - DMA3_CH1"]
+    DMA3_CH1 = 96,
+    #[doc = "97 - DMA3_CH2"]
+    DMA3_CH2 = 97,
+    #[doc = "98 - DMA3_CH3"]
+    DMA3_CH3 = 98,
+    #[doc = "99 - DMA3_CH4"]
+    DMA3_CH4 = 99,
+    #[doc = "100 - DMA3_CH5"]
+    DMA3_CH5 = 100,
+    #[doc = "101 - DMA3_CH6"]
+    DMA3_CH6 = 101,
+    #[doc = "102 - DMA3_CH7"]
+    DMA3_CH7 = 102,
+    #[doc = "103 - DMA3_CH8"]
+    DMA3_CH8 = 103,
+    #[doc = "104 - DMA3_CH9"]
+    DMA3_CH9 = 104,
+    #[doc = "105 - DMA3_CH10"]
+    DMA3_CH10 = 105,
+    #[doc = "106 - DMA3_CH11"]
+    DMA3_CH11 = 106,
+    #[doc = "107 - DMA3_CH12"]
+    DMA3_CH12 = 107,
+    #[doc = "108 - DMA3_CH13"]
+    DMA3_CH13 = 108,
+    #[doc = "109 - DMA3_CH14"]
+    DMA3_CH14 = 109,
+    #[doc = "110 - DMA3_CH15"]
+    DMA3_CH15 = 110,
+    #[doc = "111 - DMA3_CH16"]
+    DMA3_CH16 = 111,
+    #[doc = "112 - DMA3_CH17"]
+    DMA3_CH17 = 112,
+    #[doc = "113 - DMA3_CH18"]
+    DMA3_CH18 = 113,
+    #[doc = "114 - DMA3_CH19"]
+    DMA3_CH19 = 114,
+    #[doc = "115 - DMA3_CH20"]
+    DMA3_CH20 = 115,
+    #[doc = "116 - DMA3_CH21"]
+    DMA3_CH21 = 116,
+    #[doc = "117 - DMA3_CH22"]
+    DMA3_CH22 = 117,
+    #[doc = "118 - DMA3_CH23"]
+    DMA3_CH23 = 118,
+    #[doc = "119 - DMA3_CH24"]
+    DMA3_CH24 = 119,
+    #[doc = "120 - DMA3_CH25"]
+    DMA3_CH25 = 120,
+    #[doc = "121 - DMA3_CH26"]
+    DMA3_CH26 = 121,
+    #[doc = "122 - DMA3_CH27"]
+    DMA3_CH27 = 122,
+    #[doc = "123 - DMA3_CH28"]
+    DMA3_CH28 = 123,
+    #[doc = "124 - DMA3_CH29"]
+    DMA3_CH29 = 124,
+    #[doc = "125 - DMA3_CH30"]
+    DMA3_CH30 = 125,
+    #[doc = "126 - DMA3_CH31"]
+    DMA3_CH31 = 126,
+    #[doc = "127 - DMA4_ERROR"]
+    DMA4_ERROR = 127,
+    #[doc = "128 - DMA4_CH0_CH1_CH32_CH33"]
+    DMA4_CH0_CH1_CH32_CH33 = 128,
+    #[doc = "129 - DMA4_CH2_CH3_CH34_CH35"]
+    DMA4_CH2_CH3_CH34_CH35 = 129,
+    #[doc = "130 - DMA4_CH4_CH5_CH36_CH37"]
+    DMA4_CH4_CH5_CH36_CH37 = 130,
+    #[doc = "131 - DMA4_CH6_CH7_CH38_CH39"]
+    DMA4_CH6_CH7_CH38_CH39 = 131,
+    #[doc = "132 - DMA4_CH8_CH9_CH40_CH41"]
+    DMA4_CH8_CH9_CH40_CH41 = 132,
+    #[doc = "133 - DMA4_CH10_CH11_CH42_CH43"]
+    DMA4_CH10_CH11_CH42_CH43 = 133,
+    #[doc = "134 - DMA4_CH12_CH13_CH44_CH45"]
+    DMA4_CH12_CH13_CH44_CH45 = 134,
+    #[doc = "135 - DMA4_CH14_CH15_CH46_CH47"]
+    DMA4_CH14_CH15_CH46_CH47 = 135,
+    #[doc = "136 - DMA4_CH16_CH17_CH48_CH49"]
+    DMA4_CH16_CH17_CH48_CH49 = 136,
+    #[doc = "137 - DMA4_CH18_CH19_CH50_CH51"]
+    DMA4_CH18_CH19_CH50_CH51 = 137,
+    #[doc = "138 - DMA4_CH20_CH21_CH52_CH53"]
+    DMA4_CH20_CH21_CH52_CH53 = 138,
+    #[doc = "139 - DMA4_CH22_CH23_CH54_CH55"]
+    DMA4_CH22_CH23_CH54_CH55 = 139,
+    #[doc = "140 - DMA4_CH24_CH25_CH56_CH57"]
+    DMA4_CH24_CH25_CH56_CH57 = 140,
+    #[doc = "141 - DMA4_CH26_CH27_CH58_CH59"]
+    DMA4_CH26_CH27_CH58_CH59 = 141,
+    #[doc = "142 - DMA4_CH28_CH29_CH60_CH61"]
+    DMA4_CH28_CH29_CH60_CH61 = 142,
+    #[doc = "143 - DMA4_CH30_CH31_CH62_CH63"]
+    DMA4_CH30_CH31_CH62_CH63 = 143,
+    #[doc = "146 - SINC3_CH0_CH1_CH2_CH3"]
+    SINC3_CH0_CH1_CH2_CH3 = 146,
+    #[doc = "147 - EWM"]
+    EWM = 147,
+    #[doc = "148 - SEMC"]
+    SEMC = 148,
+    #[doc = "149 - LPIT3"]
+    LPIT3 = 149,
+    #[doc = "150 - LPTMR3"]
+    LPTMR3 = 150,
+    #[doc = "151 - TMR4"]
+    TMR4 = 151,
+    #[doc = "152 - LPI2C5"]
+    LPI2C5 = 152,
+    #[doc = "153 - LPI2C6"]
+    LPI2C6 = 153,
+    #[doc = "154 - SAI4"]
+    SAI4 = 154,
+    #[doc = "155 - SPDIF"]
+    SPDIF = 155,
+    #[doc = "156 - LPUART9"]
+    LPUART9 = 156,
+    #[doc = "157 - LPUART10"]
+    LPUART10 = 157,
+    #[doc = "158 - LPUART11"]
+    LPUART11 = 158,
+    #[doc = "159 - LPUART12"]
+    LPUART12 = 159,
+    #[doc = "164 - TMR3"]
+    TMR3 = 164,
+    #[doc = "170 - PWM2_FAULT"]
+    PWM2_FAULT = 170,
+    #[doc = "171 - PWM2_0"]
+    PWM2_0 = 171,
+    #[doc = "172 - PWM2_1"]
+    PWM2_1 = 172,
+    #[doc = "173 - PWM2_2"]
+    PWM2_2 = 173,
+    #[doc = "174 - PWM2_3"]
+    PWM2_3 = 174,
+    #[doc = "175 - PWM3_FAULT"]
+    PWM3_FAULT = 175,
+    #[doc = "176 - PWM3_0"]
+    PWM3_0 = 176,
+    #[doc = "177 - PWM3_1"]
+    PWM3_1 = 177,
+    #[doc = "178 - PWM3_2"]
+    PWM3_2 = 178,
+    #[doc = "179 - PWM3_3"]
+    PWM3_3 = 179,
+    #[doc = "180 - PWM4_FAULT"]
+    PWM4_FAULT = 180,
+    #[doc = "181 - PWM4_0"]
+    PWM4_0 = 181,
+    #[doc = "182 - PWM4_1"]
+    PWM4_1 = 182,
+    #[doc = "183 - PWM4_2"]
+    PWM4_2 = 183,
+    #[doc = "184 - PWM4_3"]
+    PWM4_3 = 184,
+    #[doc = "185 - EQDC1"]
+    EQDC1 = 185,
+    #[doc = "186 - EQDC2"]
+    EQDC2 = 186,
+    #[doc = "187 - EQDC3"]
+    EQDC3 = 187,
+    #[doc = "188 - EQDC4"]
+    EQDC4 = 188,
+    #[doc = "189 - ADC2"]
+    ADC2 = 189,
+    #[doc = "190 - DCDC"]
+    DCDC = 190,
+    #[doc = "191 - CAN3"]
+    CAN3 = 191,
+    #[doc = "192 - CAN3_ERROR"]
+    CAN3_ERROR = 192,
+    #[doc = "193 - DAC"]
+    DAC = 193,
+    #[doc = "194 - LPSPI5"]
+    LPSPI5 = 194,
+    #[doc = "195 - LPSPI6"]
+    LPSPI6 = 195,
+    #[doc = "196 - LPUART7"]
+    LPUART7 = 196,
+    #[doc = "197 - LPUART8"]
+    LPUART8 = 197,
+    #[doc = "198 - SAI2"]
+    SAI2 = 198,
+    #[doc = "199 - SAI3"]
+    SAI3 = 199,
+    #[doc = "200 - ACMP1"]
+    ACMP1 = 200,
+    #[doc = "201 - ACMP2"]
+    ACMP2 = 201,
+    #[doc = "202 - ACMP3"]
+    ACMP3 = 202,
+    #[doc = "203 - ACMP4"]
+    ACMP4 = 203,
+    #[doc = "209 - GPT1"]
+    GPT1 = 209,
+    #[doc = "210 - GPT2"]
+    GPT2 = 210,
+    #[doc = "211 - KPP"]
+    KPP = 211,
+    #[doc = "212 - USBPHY1"]
+    USBPHY1 = 212,
+    #[doc = "213 - USBPHY2"]
+    USBPHY2 = 213,
+    #[doc = "214 - USB_OTG2"]
+    USB_OTG2 = 214,
+    #[doc = "215 - USB_OTG1"]
+    USB_OTG1 = 215,
+    #[doc = "224 - SINC1_CH0"]
+    SINC1_CH0 = 224,
+    #[doc = "225 - SINC1_CH1"]
+    SINC1_CH1 = 225,
+    #[doc = "226 - SINC1_CH2"]
+    SINC1_CH2 = 226,
+    #[doc = "227 - SINC1_CH3"]
+    SINC1_CH3 = 227,
+    #[doc = "228 - SINC2_CH0"]
+    SINC2_CH0 = 228,
+    #[doc = "229 - SINC2_CH1"]
+    SINC2_CH1 = 229,
+    #[doc = "230 - SINC2_CH2"]
+    SINC2_CH2 = 230,
+    #[doc = "231 - SINC2_CH3"]
+    SINC2_CH3 = 231,
+    #[doc = "232 - GPIO4"]
+    GPIO4 = 232,
+    #[doc = "233 - TMR2"]
+    TMR2 = 233,
+    #[doc = "234 - GPIO5"]
+    GPIO5 = 234,
+    #[doc = "235 - ASRC"]
+    ASRC = 235,
+    #[doc = "236 - GPIO6"]
+    GPIO6 = 236,
+}
+pub type interrupt = Interrupt;
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+
+mod _vectors {
+    unsafe extern "C" {
+        fn TMR1();
+        fn TMR5();
+        fn TMR6();
+        fn TMR7();
+        fn TMR8();
+        fn CAN1();
+        fn CAN1_ERROR();
+        fn GPIO1_0();
+        fn GPIO1_1();
+        fn I3C1();
+        fn LPI2C1();
+        fn LPI2C2();
+        fn LPIT1();
+        fn LPSPI1();
+        fn LPSPI2();
+        fn LPTMR1();
+        fn LPUART1();
+        fn LPUART2();
+        fn MU1();
+        fn MU2();
+        fn PWM1_FAULT();
+        fn PWM1_0();
+        fn PWM1_1();
+        fn PWM1_2();
+        fn PWM1_3();
+        fn TPM1();
+        fn TPM2();
+        fn RTWDOG1();
+        fn RTWDOG2();
+        fn TRDC_MGR_AON();
+        fn PDM_HWVAD_EVENT();
+        fn PDM_HWVAD_ERROR();
+        fn PDM_EVENT();
+        fn PDM_ERROR();
+        fn SAI1();
+        fn CAN2();
+        fn CAN2_ERROR();
+        fn FLEXIO1();
+        fn FLEXIO2();
+        fn FLEXSPI1();
+        fn FLEXSPI2();
+        fn GPIO2_0();
+        fn GPIO2_1();
+        fn GPIO3_0();
+        fn GPIO3_1();
+        fn I3C2();
+        fn LPI2C3();
+        fn LPI2C4();
+        fn LPIT2();
+        fn LPSPI3();
+        fn LPSPI4();
+        fn LPTMR2();
+        fn LPUART3();
+        fn LPUART4();
+        fn LPUART5();
+        fn LPUART6();
+        fn BBNSM();
+        fn TPM3();
+        fn TPM4();
+        fn TPM5();
+        fn TPM6();
+        fn RTWDOG3();
+        fn RTWDOG4();
+        fn RTWDOG5();
+        fn TRDC_MGR_WKUP();
+        fn USDHC1();
+        fn USDHC2();
+        fn TRDC_MGR_MEGA();
+        fn ADC1();
+        fn DMA_ERROR();
+        fn DMA3_CH0();
+        fn DMA3_CH1();
+        fn DMA3_CH2();
+        fn DMA3_CH3();
+        fn DMA3_CH4();
+        fn DMA3_CH5();
+        fn DMA3_CH6();
+        fn DMA3_CH7();
+        fn DMA3_CH8();
+        fn DMA3_CH9();
+        fn DMA3_CH10();
+        fn DMA3_CH11();
+        fn DMA3_CH12();
+        fn DMA3_CH13();
+        fn DMA3_CH14();
+        fn DMA3_CH15();
+        fn DMA3_CH16();
+        fn DMA3_CH17();
+        fn DMA3_CH18();
+        fn DMA3_CH19();
+        fn DMA3_CH20();
+        fn DMA3_CH21();
+        fn DMA3_CH22();
+        fn DMA3_CH23();
+        fn DMA3_CH24();
+        fn DMA3_CH25();
+        fn DMA3_CH26();
+        fn DMA3_CH27();
+        fn DMA3_CH28();
+        fn DMA3_CH29();
+        fn DMA3_CH30();
+        fn DMA3_CH31();
+        fn DMA4_ERROR();
+        fn DMA4_CH0_CH1_CH32_CH33();
+        fn DMA4_CH2_CH3_CH34_CH35();
+        fn DMA4_CH4_CH5_CH36_CH37();
+        fn DMA4_CH6_CH7_CH38_CH39();
+        fn DMA4_CH8_CH9_CH40_CH41();
+        fn DMA4_CH10_CH11_CH42_CH43();
+        fn DMA4_CH12_CH13_CH44_CH45();
+        fn DMA4_CH14_CH15_CH46_CH47();
+        fn DMA4_CH16_CH17_CH48_CH49();
+        fn DMA4_CH18_CH19_CH50_CH51();
+        fn DMA4_CH20_CH21_CH52_CH53();
+        fn DMA4_CH22_CH23_CH54_CH55();
+        fn DMA4_CH24_CH25_CH56_CH57();
+        fn DMA4_CH26_CH27_CH58_CH59();
+        fn DMA4_CH28_CH29_CH60_CH61();
+        fn DMA4_CH30_CH31_CH62_CH63();
+        fn SINC3_CH0_CH1_CH2_CH3();
+        fn EWM();
+        fn SEMC();
+        fn LPIT3();
+        fn LPTMR3();
+        fn TMR4();
+        fn LPI2C5();
+        fn LPI2C6();
+        fn SAI4();
+        fn SPDIF();
+        fn LPUART9();
+        fn LPUART10();
+        fn LPUART11();
+        fn LPUART12();
+        fn TMR3();
+        fn PWM2_FAULT();
+        fn PWM2_0();
+        fn PWM2_1();
+        fn PWM2_2();
+        fn PWM2_3();
+        fn PWM3_FAULT();
+        fn PWM3_0();
+        fn PWM3_1();
+        fn PWM3_2();
+        fn PWM3_3();
+        fn PWM4_FAULT();
+        fn PWM4_0();
+        fn PWM4_1();
+        fn PWM4_2();
+        fn PWM4_3();
+        fn EQDC1();
+        fn EQDC2();
+        fn EQDC3();
+        fn EQDC4();
+        fn ADC2();
+        fn DCDC();
+        fn CAN3();
+        fn CAN3_ERROR();
+        fn DAC();
+        fn LPSPI5();
+        fn LPSPI6();
+        fn LPUART7();
+        fn LPUART8();
+        fn SAI2();
+        fn SAI3();
+        fn ACMP1();
+        fn ACMP2();
+        fn ACMP3();
+        fn ACMP4();
+        fn GPT1();
+        fn GPT2();
+        fn KPP();
+        fn USBPHY1();
+        fn USBPHY2();
+        fn USB_OTG2();
+        fn USB_OTG1();
+        fn SINC1_CH0();
+        fn SINC1_CH1();
+        fn SINC1_CH2();
+        fn SINC1_CH3();
+        fn SINC2_CH0();
+        fn SINC2_CH1();
+        fn SINC2_CH2();
+        fn SINC2_CH3();
+        fn GPIO4();
+        fn TMR2();
+        fn GPIO5();
+        fn ASRC();
+        fn GPIO6();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".vector_table.interrupts"))]
+    #[unsafe(no_mangle)]
+    pub static __INTERRUPTS: [Vector; 237] = [
+        Vector { _handler: TMR1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TMR5 },
+        Vector { _handler: TMR6 },
+        Vector { _handler: TMR7 },
+        Vector { _handler: TMR8 },
+        Vector { _handler: CAN1 },
+        Vector {
+            _handler: CAN1_ERROR,
+        },
+        Vector { _handler: GPIO1_0 },
+        Vector { _handler: GPIO1_1 },
+        Vector { _handler: I3C1 },
+        Vector { _handler: LPI2C1 },
+        Vector { _handler: LPI2C2 },
+        Vector { _handler: LPIT1 },
+        Vector { _handler: LPSPI1 },
+        Vector { _handler: LPSPI2 },
+        Vector { _handler: LPTMR1 },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: LPUART2 },
+        Vector { _handler: MU1 },
+        Vector { _handler: MU2 },
+        Vector {
+            _handler: PWM1_FAULT,
+        },
+        Vector { _handler: PWM1_0 },
+        Vector { _handler: PWM1_1 },
+        Vector { _handler: PWM1_2 },
+        Vector { _handler: PWM1_3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TPM1 },
+        Vector { _handler: TPM2 },
+        Vector { _handler: RTWDOG1 },
+        Vector { _handler: RTWDOG2 },
+        Vector {
+            _handler: TRDC_MGR_AON,
+        },
+        Vector {
+            _handler: PDM_HWVAD_EVENT,
+        },
+        Vector {
+            _handler: PDM_HWVAD_ERROR,
+        },
+        Vector {
+            _handler: PDM_EVENT,
+        },
+        Vector {
+            _handler: PDM_ERROR,
+        },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2 },
+        Vector {
+            _handler: CAN2_ERROR,
+        },
+        Vector { _handler: FLEXIO1 },
+        Vector { _handler: FLEXIO2 },
+        Vector { _handler: FLEXSPI1 },
+        Vector { _handler: FLEXSPI2 },
+        Vector { _handler: GPIO2_0 },
+        Vector { _handler: GPIO2_1 },
+        Vector { _handler: GPIO3_0 },
+        Vector { _handler: GPIO3_1 },
+        Vector { _handler: I3C2 },
+        Vector { _handler: LPI2C3 },
+        Vector { _handler: LPI2C4 },
+        Vector { _handler: LPIT2 },
+        Vector { _handler: LPSPI3 },
+        Vector { _handler: LPSPI4 },
+        Vector { _handler: LPTMR2 },
+        Vector { _handler: LPUART3 },
+        Vector { _handler: LPUART4 },
+        Vector { _handler: LPUART5 },
+        Vector { _handler: LPUART6 },
+        Vector { _reserved: 0 },
+        Vector { _handler: BBNSM },
+        Vector { _reserved: 0 },
+        Vector { _handler: TPM3 },
+        Vector { _handler: TPM4 },
+        Vector { _handler: TPM5 },
+        Vector { _handler: TPM6 },
+        Vector { _handler: RTWDOG3 },
+        Vector { _handler: RTWDOG4 },
+        Vector { _handler: RTWDOG5 },
+        Vector {
+            _handler: TRDC_MGR_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: USDHC1 },
+        Vector { _handler: USDHC2 },
+        Vector {
+            _handler: TRDC_MGR_MEGA,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: ADC1 },
+        Vector {
+            _handler: DMA_ERROR,
+        },
+        Vector { _handler: DMA3_CH0 },
+        Vector { _handler: DMA3_CH1 },
+        Vector { _handler: DMA3_CH2 },
+        Vector { _handler: DMA3_CH3 },
+        Vector { _handler: DMA3_CH4 },
+        Vector { _handler: DMA3_CH5 },
+        Vector { _handler: DMA3_CH6 },
+        Vector { _handler: DMA3_CH7 },
+        Vector { _handler: DMA3_CH8 },
+        Vector { _handler: DMA3_CH9 },
+        Vector {
+            _handler: DMA3_CH10,
+        },
+        Vector {
+            _handler: DMA3_CH11,
+        },
+        Vector {
+            _handler: DMA3_CH12,
+        },
+        Vector {
+            _handler: DMA3_CH13,
+        },
+        Vector {
+            _handler: DMA3_CH14,
+        },
+        Vector {
+            _handler: DMA3_CH15,
+        },
+        Vector {
+            _handler: DMA3_CH16,
+        },
+        Vector {
+            _handler: DMA3_CH17,
+        },
+        Vector {
+            _handler: DMA3_CH18,
+        },
+        Vector {
+            _handler: DMA3_CH19,
+        },
+        Vector {
+            _handler: DMA3_CH20,
+        },
+        Vector {
+            _handler: DMA3_CH21,
+        },
+        Vector {
+            _handler: DMA3_CH22,
+        },
+        Vector {
+            _handler: DMA3_CH23,
+        },
+        Vector {
+            _handler: DMA3_CH24,
+        },
+        Vector {
+            _handler: DMA3_CH25,
+        },
+        Vector {
+            _handler: DMA3_CH26,
+        },
+        Vector {
+            _handler: DMA3_CH27,
+        },
+        Vector {
+            _handler: DMA3_CH28,
+        },
+        Vector {
+            _handler: DMA3_CH29,
+        },
+        Vector {
+            _handler: DMA3_CH30,
+        },
+        Vector {
+            _handler: DMA3_CH31,
+        },
+        Vector {
+            _handler: DMA4_ERROR,
+        },
+        Vector {
+            _handler: DMA4_CH0_CH1_CH32_CH33,
+        },
+        Vector {
+            _handler: DMA4_CH2_CH3_CH34_CH35,
+        },
+        Vector {
+            _handler: DMA4_CH4_CH5_CH36_CH37,
+        },
+        Vector {
+            _handler: DMA4_CH6_CH7_CH38_CH39,
+        },
+        Vector {
+            _handler: DMA4_CH8_CH9_CH40_CH41,
+        },
+        Vector {
+            _handler: DMA4_CH10_CH11_CH42_CH43,
+        },
+        Vector {
+            _handler: DMA4_CH12_CH13_CH44_CH45,
+        },
+        Vector {
+            _handler: DMA4_CH14_CH15_CH46_CH47,
+        },
+        Vector {
+            _handler: DMA4_CH16_CH17_CH48_CH49,
+        },
+        Vector {
+            _handler: DMA4_CH18_CH19_CH50_CH51,
+        },
+        Vector {
+            _handler: DMA4_CH20_CH21_CH52_CH53,
+        },
+        Vector {
+            _handler: DMA4_CH22_CH23_CH54_CH55,
+        },
+        Vector {
+            _handler: DMA4_CH24_CH25_CH56_CH57,
+        },
+        Vector {
+            _handler: DMA4_CH26_CH27_CH58_CH59,
+        },
+        Vector {
+            _handler: DMA4_CH28_CH29_CH60_CH61,
+        },
+        Vector {
+            _handler: DMA4_CH30_CH31_CH62_CH63,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: SINC3_CH0_CH1_CH2_CH3,
+        },
+        Vector { _handler: EWM },
+        Vector { _handler: SEMC },
+        Vector { _handler: LPIT3 },
+        Vector { _handler: LPTMR3 },
+        Vector { _handler: TMR4 },
+        Vector { _handler: LPI2C5 },
+        Vector { _handler: LPI2C6 },
+        Vector { _handler: SAI4 },
+        Vector { _handler: SPDIF },
+        Vector { _handler: LPUART9 },
+        Vector { _handler: LPUART10 },
+        Vector { _handler: LPUART11 },
+        Vector { _handler: LPUART12 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TMR3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: PWM2_FAULT,
+        },
+        Vector { _handler: PWM2_0 },
+        Vector { _handler: PWM2_1 },
+        Vector { _handler: PWM2_2 },
+        Vector { _handler: PWM2_3 },
+        Vector {
+            _handler: PWM3_FAULT,
+        },
+        Vector { _handler: PWM3_0 },
+        Vector { _handler: PWM3_1 },
+        Vector { _handler: PWM3_2 },
+        Vector { _handler: PWM3_3 },
+        Vector {
+            _handler: PWM4_FAULT,
+        },
+        Vector { _handler: PWM4_0 },
+        Vector { _handler: PWM4_1 },
+        Vector { _handler: PWM4_2 },
+        Vector { _handler: PWM4_3 },
+        Vector { _handler: EQDC1 },
+        Vector { _handler: EQDC2 },
+        Vector { _handler: EQDC3 },
+        Vector { _handler: EQDC4 },
+        Vector { _handler: ADC2 },
+        Vector { _handler: DCDC },
+        Vector { _handler: CAN3 },
+        Vector {
+            _handler: CAN3_ERROR,
+        },
+        Vector { _handler: DAC },
+        Vector { _handler: LPSPI5 },
+        Vector { _handler: LPSPI6 },
+        Vector { _handler: LPUART7 },
+        Vector { _handler: LPUART8 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SAI3 },
+        Vector { _handler: ACMP1 },
+        Vector { _handler: ACMP2 },
+        Vector { _handler: ACMP3 },
+        Vector { _handler: ACMP4 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: GPT1 },
+        Vector { _handler: GPT2 },
+        Vector { _handler: KPP },
+        Vector { _handler: USBPHY1 },
+        Vector { _handler: USBPHY2 },
+        Vector { _handler: USB_OTG2 },
+        Vector { _handler: USB_OTG1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: SINC1_CH0,
+        },
+        Vector {
+            _handler: SINC1_CH1,
+        },
+        Vector {
+            _handler: SINC1_CH2,
+        },
+        Vector {
+            _handler: SINC1_CH3,
+        },
+        Vector {
+            _handler: SINC2_CH0,
+        },
+        Vector {
+            _handler: SINC2_CH1,
+        },
+        Vector {
+            _handler: SINC2_CH2,
+        },
+        Vector {
+            _handler: SINC2_CH3,
+        },
+        Vector { _handler: GPIO4 },
+        Vector { _handler: TMR2 },
+        Vector { _handler: GPIO5 },
+        Vector { _handler: ASRC },
+        Vector { _handler: GPIO6 },
+    ];
+}