diff options
Diffstat (limited to 'imxrt1010/src/lib.rs')
| -rw-r--r-- | imxrt1010/src/lib.rs | 37 |
1 files changed, 35 insertions, 2 deletions
diff --git a/imxrt1010/src/lib.rs b/imxrt1010/src/lib.rs index 820e51f..873dd58 100644 --- a/imxrt1010/src/lib.rs +++ b/imxrt1010/src/lib.rs @@ -2,7 +2,8 @@ #![no_std] pub use imxrt_flash_algos::*; -use imxrt1010::{ccm, dcdc, instances}; +use imxrt1010::{ccm, dcdc, instances, iomuxc}; +use ral_registers as ral; pub struct Imxrt1010; impl imxrt10xx::Imxrt10xx for Imxrt1010 { @@ -16,6 +17,9 @@ impl imxrt10xx::Imxrt10xx for Imxrt1010 { const FLEXSPI_FIFO_CAPACITY_BYTES: usize = 128; + type IOMUXC = imxrt1010::iomuxc::Instance; + const IOMUXC_INSTANCE: Self::IOMUXC = unsafe { instances::iomuxc() }; + fn configure_clocks(ccm: ccm::CCM, ccm_analog: ccm::CCM_ANALOG, dcdc: dcdc::Instance) { dcdc::set_target_vdd_soc(dcdc, 1250); @@ -23,11 +27,40 @@ impl imxrt10xx::Imxrt10xx for Imxrt1010 { ccm::pll3::restart(ccm_analog); - ccm::flexspi1_clk::set_divider(ccm, 4); + ccm::flexspi1_clk::set_divider(ccm, 8); ccm::flexspi1_clk::set_selection(ccm, ccm::flexspi1_clk::Selection::Pll3); ccm::clock_gate::set(ccm, ccm::gates::FLEXSPI, true.into()); } + + fn configure_pins(iomuxc: Self::IOMUXC) { + use iomuxc::{pad, select_input}; + + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_12], MUX_MODE: 0, SION: 1); // DQS + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_06], MUX_MODE: 0, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_05], MUX_MODE: 0, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_10], MUX_MODE: 0, SION: 1); // SCK + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_09], MUX_MODE: 0, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_07], MUX_MODE: 0, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_08], MUX_MODE: 0, SION: 0); + ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_11], MUX_MODE: 0, SION: 0); + + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_12], PUE: 1, PKE: 1, SPEED: MEDIUM_100MHZ, DSE: R0, PUS: PD_100K_OHM); // DQS + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_06], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_05], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_10], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_09], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_07], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_08], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_11], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0); + + ral::write_reg!( + iomuxc, + iomuxc, + SELECT_INPUT[select_input::FLEXSPI_DQS_FA], + 1 + ); + } } pub type Algorithm<const FLASH_SIZE_BYTES: usize> = |