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//! Interface package for writing flash algorithms for 1010 MCUs.
#![no_std]
pub use imxrt_flash_algos::*;
use imxrt1010::{ccm, dcdc, instances, iomuxc};
use ral_registers as ral;
pub struct Imxrt1010;
impl imxrt10xx::Imxrt10xx for Imxrt1010 {
const FLEXSPI1_INSTANCE: imxrt1010::flexspi::Instance = unsafe { instances::flexspi() };
const CCM_INSTANCE: ccm::CCM = unsafe { instances::ccm() };
const CCM_ANALOG_INSTANCE: ccm::CCM_ANALOG = unsafe { instances::ccm_analog() };
const DCDC_INSTANCE: dcdc::Instance = unsafe { instances::dcdc() };
const FLEXSPI_FIFO_CAPACITY_BYTES: usize = 128;
type IOMUXC = imxrt1010::iomuxc::Instance;
const IOMUXC_INSTANCE: Self::IOMUXC = unsafe { instances::iomuxc() };
fn configure_clocks(ccm: ccm::CCM, ccm_analog: ccm::CCM_ANALOG, dcdc: dcdc::Instance) {
dcdc::set_target_vdd_soc(dcdc, 1250);
ccm::clock_gate::set(ccm, ccm::gates::FLEXSPI, false.into());
ccm::pll3::restart(ccm_analog);
ccm::flexspi1_clk::set_divider(ccm, 8);
ccm::flexspi1_clk::set_selection(ccm, ccm::flexspi1_clk::Selection::Pll3);
ccm::clock_gate::set(ccm, ccm::gates::FLEXSPI, true.into());
}
fn configure_pins(iomuxc: Self::IOMUXC) {
use iomuxc::{pad, select_input};
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_12], MUX_MODE: 0, SION: 1); // DQS
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_06], MUX_MODE: 0, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_05], MUX_MODE: 0, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_10], MUX_MODE: 0, SION: 1); // SCK
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_09], MUX_MODE: 0, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_07], MUX_MODE: 0, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_08], MUX_MODE: 0, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_MUX_CTL_PAD[pad::GPIO_SD_11], MUX_MODE: 0, SION: 0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_12], PUE: 1, PKE: 1, SPEED: MEDIUM_100MHZ, DSE: R0, PUS: PD_100K_OHM); // DQS
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_06], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_05], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_10], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_09], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_07], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_08], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(iomuxc, iomuxc, SW_PAD_CTL_PAD[pad::GPIO_SD_11], PUE: 0, PKE: 0, SPEED: MEDIUM_100MHZ, DSE: R0);
ral::write_reg!(
iomuxc,
iomuxc,
SELECT_INPUT[select_input::FLEXSPI_DQS_FA],
1
);
}
}
pub type Algorithm<const FLASH_SIZE_BYTES: usize> =
imxrt10xx::Algorithm<Imxrt1010, FLASH_SIZE_BYTES>;
|
