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| author | ECP5-PCIe <65254322+ECP5-PCIe@users.noreply.github.com> | 2020-07-16 10:22:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-16 08:22:51 +0000 |
| commit | 19cf06052230831e6d899aa3cf71539fe746a43e (patch) | |
| tree | 6d138b34c46a822239879d31fc9d99b4e15b7a52 /nmigen_boards/mercury.py | |
| parent | 83d9ecdd47e6610ea71037e155a8e2fd51f9f19c (diff) | |
[breaking-change] Update SPI pin names.
The new names follow the OSHWA convention described at:
https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
Diffstat (limited to 'nmigen_boards/mercury.py')
| -rw-r--r-- | nmigen_boards/mercury.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/nmigen_boards/mercury.py b/nmigen_boards/mercury.py index 5daf802..c0bd107 100644 --- a/nmigen_boards/mercury.py +++ b/nmigen_boards/mercury.py @@ -40,19 +40,19 @@ class MercuryPlatform(XilinxSpartan3APlatform): # The serial interface and flash memory have a shared SPI bus. # FPGA is secondary. SPIResource("spi_serial", 0, role="device", - cs="P39", clk="P53", mosi="P46", miso="P51", + cs="P39", clk="P53", copi="P46", cipo="P51", attrs=Attrs(IOSTANDARD="LVTTL"), ), # FPGA is primary. *SPIFlashResources(0, - cs="P27", clk="P53", mosi="P46", miso="P51", + cs="P27", clk="P53", copi="P46", cipo="P51", attrs=Attrs(IOSTANDARD="LVTTL") ), # ADC over SPI- FPGA is primary. SPIResource("spi_adc", 0, role="host", - cs="P12", clk="P9", mosi="P10", miso="P21", + cs="P12", clk="P9", copi="P10", cipo="P21", attrs=Attrs(IOSTANDARD="LVTTL"), ), |