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2021-06-05[breaking-change] de10_lite: fix clk50 numbering.S.J.R. van Schaik
2021-06-05mercury: specify attrs key when defining the VGAResourceS.J.R. van Schaik
2021-06-04nandland_go: add Nandland Go platform.S.J.R. van Schaik
2021-06-03[breaking-change] Factor out PS2Resource.S.J.R. van Schaik
2021-05-31[breaking-change] Factor out VGAResource.S.J.R. van Schaik
2021-05-30arty_a7: support both the 35T and 100T SKUsS.J.R. van Schaik
2021-02-24arty_a7: add missing constraintsslan
2021-02-15ulx3s: fix pin mapping for audio at ring 2martinbarez
2021-01-31ecpix-5: ddr3: Adjust IO_TYPE attribute to match VCCIO which is 1.5v for ↵Vadzim Dambrouski
this board. This is not a functional change because both SSTL135 and SSTL15 generate identical bitcode. But it will hopefully prevent some confusion and will match the litex_boards config.
2021-01-31ecpix-5: ddr3: Add missing address pin.Vadzim Dambrouski
2021-01-31ecpix-5: ddr3: Add missing SLEWRATE="FAST" attributeVadzim Dambrouski
2020-12-28arty_s7: fix blinky built-in test.whitequark
2020-11-26[breaking-change] Add `_n` suffix to argument names of pins with fixed ↵GuzTech
inverters. Note: this change does NOT affect pin functionality or naming, and does not require modifying your design. It does however affect some board files, where keywords corresponding to active low pins will have to be adjusted: SPIResource(0, cs="C1", ...) → SPIResource(0, cs_n="C1", ...) The new naming scheme will make it easier to write and audit board files by clearly marking inverted pins in resource factories, similarly to how `PinsN` indicates the same in bare resources. Fixes #129.
2020-11-25Add RZ-EasyFPGA A2.2.Móricz Gergő
2020-11-25resources.interface: allow SPIResource to be unidirectional.whitequark
See #104.
2020-11-24Add TE0714-03-50-2IRobin Ole Heinemann
2020-11-24ulx3s: add HDMI pins.GuzTech
This commit adds the HDMI (called GDPI for licensing reasons) pins to the ULX3S platform. The constraints were taken from https://github.com/emard/ulx3s-misc/blob/master/constraints/ulx3s_v20.lpf The top bank of the ECP5 only support differential outputs, so make all differential pairs outputs.
2020-11-24Add Chameleon96 support.Konrad Beckmann
2020-11-24Add DE1-SoC support.H-S-S-11
2020-11-13Add Quickfeather.Jan Kowalewski
Co-authored-by: whitequark <whitequark@whitequark.org> Co-Authored-By: Kamil Rakoczy <krakoczy@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2020-11-13Use importlib_metadata instead of pkg_resources.whitequark
2020-11-05Factor out I2C resource.awygle
2020-10-15arty_s7: add openocd and flashing support.William D. Jones
2020-10-09genesys2: convert `ulpi` to ULPIResourceKatherine Temkin
2020-10-09genesys2: correctly specify I/O attributes for VADJ banksKatherine Temkin
2020-09-21ulx3s: fix copy-paste error in GPIO mappings.Thomas Daede
2020-09-13ulx3s: correct speed grade.Thomas Daede
The boards available on the crowdsupply page, as well as my hand-built board, all seem to use speed grade 6.
2020-09-06resources.memory: make cs pin optional for SDRAMResourcemarble
2020-08-26arty_z7: fix PMOD 1 (JB) pinout.DaKnig
2020-08-25arty_a7: fix `rst` pin polarity.Mariusz Glebocki
2020-08-17Added Arty S7 supportStaf Verhaegen
This is based on Arty A7 file. Some things are handled differently: * Rename cpu_reset resource to rst and use it as default circuit reset. * Use Vivado for programming the board. * Don't overload .bin generation; it does not seem to make a difference. * Generate also mcs file. This is used by openFPGALoader for programming into SPI Flash. Arty S7-50 has been tested on the board by blinky test; Arty S7-25 only bitstream generation, not on the board.
2020-08-15Use correct IO attribute for ECP5 FPGAsOguz Meteer
This changes several incorrect IO_STANDARD attributes to IO_TYPE. Signed-off-by: Oguz Meteer <info@guztech.nl>
2020-08-10[breaking-change] Arty A7: rename cpu_reset resource to rst. (#102)Staf Verhaegen
It's now define properly as input and used as default reset.
2020-08-07versa_ecp5: Fix DDR3 IO types, using the types from Lattice's DDR3 demo lpfJean THOMAS
2020-08-06resources: allow use of ULPI PHYs with active-low RST pinsKatherine Temkin
Also, fixes a typo that affected PHYs with rst specified
2020-08-06Add Hackaday Supercon19Badge.Katherine Temkin
2020-08-05Add MicroZed Z010 and Z020.Robin Heinemann
2020-08-03ecpix5: add termination attributes to DDR3 signalsJean THOMAS
2020-07-28Add iCEBreaker Bitsy.Kate Temkin
2020-07-27Add ULX3S.Kate Temkin
2020-07-27orangecrab_r0_2: fix sense diffpair.Joshua Koike
2020-07-27orangecrab_r0_2: convert sense to diffpairJoshua Koike
2020-07-22tinyfpga_axN: use vendor.lattice_machxo2, not .lattice_machxo_2_3l.whitequark
This restores compatibility with nMigen 0.2.
2020-07-21fomu_pvt: fix typoRobin Ole Heinemann
2020-07-19Factor out direct USB and ULPI resources.Kate Temkin
2020-07-18mercury: fix SPI rolesRobin Ole Heinemann
2020-07-16ecpix5: fix PMOD4 pins.Jean-François Nguyen
2020-07-16[breaking-change] Update SPI pin names.ECP5-PCIe
The new names follow the OSHWA convention described at: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
2020-07-15Add OrangeCrab r0.1Mike Walters
2020-07-14orangecrab_r0_2: fix dq pin definitions.Mike Walters
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-26 23:35:37 +0000