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-rw-r--r--chips/imxrt1010/Cargo.toml17
-rw-r--r--chips/imxrt1010/build.rs8
-rw-r--r--chips/imxrt1010/device.x74
-rw-r--r--chips/imxrt1010/src/iomuxc.rs100
-rw-r--r--chips/imxrt1010/src/lib.rs76
-rw-r--r--chips/imxrt1010/src/rt.rs361
6 files changed, 636 insertions, 0 deletions
diff --git a/chips/imxrt1010/Cargo.toml b/chips/imxrt1010/Cargo.toml
new file mode 100644
index 0000000..2a00927
--- /dev/null
+++ b/chips/imxrt1010/Cargo.toml
@@ -0,0 +1,17 @@
+[package]
+name = "imxrt1010"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+cortex-m = { workspace = true }
+ral-registers = { workspace = true }
+
+imxrt-drivers-ccm-10xx = { workspace = true }
+imxrt-drivers-dcdc = { workspace = true }
+imxrt-drivers-gpio = { workspace = true }
+imxrt-drivers-flexspi = { workspace = true }
+imxrt-drivers-iomuxc-10xx = { workspace = true }
+imxrt-drivers-lpspi = { workspace = true }
+imxrt-drivers-pit = { workspace = true }
+imxrt-drivers-rtwdog = { workspace = true }
diff --git a/chips/imxrt1010/build.rs b/chips/imxrt1010/build.rs
new file mode 100644
index 0000000..3af590f
--- /dev/null
+++ b/chips/imxrt1010/build.rs
@@ -0,0 +1,8 @@
+use std::{env, fs, path};
+
+fn main() {
+ let out_dir = path::PathBuf::from(env::var("OUT_DIR").unwrap());
+ fs::copy("device.x", out_dir.join("device.x")).unwrap();
+ fs::copy("device.x", out_dir.join("imxrt1010.x")).unwrap();
+ println!("cargo::rustc-link-search={}", out_dir.display());
+}
diff --git a/chips/imxrt1010/device.x b/chips/imxrt1010/device.x
new file mode 100644
index 0000000..1d52693
--- /dev/null
+++ b/chips/imxrt1010/device.x
@@ -0,0 +1,74 @@
+PROVIDE(DMA0 = DefaultHandler);
+PROVIDE(DMA1 = DefaultHandler);
+PROVIDE(DMA2 = DefaultHandler);
+PROVIDE(DMA3 = DefaultHandler);
+PROVIDE(DMA4 = DefaultHandler);
+PROVIDE(DMA5 = DefaultHandler);
+PROVIDE(DMA6 = DefaultHandler);
+PROVIDE(DMA7 = DefaultHandler);
+PROVIDE(DMA8 = DefaultHandler);
+PROVIDE(DMA9 = DefaultHandler);
+PROVIDE(DMA10 = DefaultHandler);
+PROVIDE(DMA11 = DefaultHandler);
+PROVIDE(DMA12 = DefaultHandler);
+PROVIDE(DMA13 = DefaultHandler);
+PROVIDE(DMA14 = DefaultHandler);
+PROVIDE(DMA15 = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(LPUART1 = DefaultHandler);
+PROVIDE(LPUART2 = DefaultHandler);
+PROVIDE(LPUART3 = DefaultHandler);
+PROVIDE(LPUART4 = DefaultHandler);
+PROVIDE(PIT = DefaultHandler);
+PROVIDE(USB_OTG1 = DefaultHandler);
+PROVIDE(FLEXSPI = DefaultHandler);
+PROVIDE(FLEXRAM = DefaultHandler);
+PROVIDE(LPI2C1 = DefaultHandler);
+PROVIDE(LPI2C2 = DefaultHandler);
+PROVIDE(GPT1 = DefaultHandler);
+PROVIDE(GPT2 = DefaultHandler);
+PROVIDE(LPSPI1 = DefaultHandler);
+PROVIDE(LPSPI2 = DefaultHandler);
+PROVIDE(PWM1_0 = DefaultHandler);
+PROVIDE(PWM1_1 = DefaultHandler);
+PROVIDE(PWM1_2 = DefaultHandler);
+PROVIDE(PWM1_3 = DefaultHandler);
+PROVIDE(PWM1_FAULT = DefaultHandler);
+PROVIDE(KPP = DefaultHandler);
+PROVIDE(SRC = DefaultHandler);
+PROVIDE(GPR_IRQ = DefaultHandler);
+PROVIDE(CCM_1 = DefaultHandler);
+PROVIDE(CCM_2 = DefaultHandler);
+PROVIDE(EWM = DefaultHandler);
+PROVIDE(WDOG2 = DefaultHandler);
+PROVIDE(SNVS_HP_WRAPPER = DefaultHandler);
+PROVIDE(SNVS_HP_WRAPPER_TZ = DefaultHandler);
+PROVIDE(SNVS_LP_WRAPPER = DefaultHandler);
+PROVIDE(CSU = DefaultHandler);
+PROVIDE(DCP = DefaultHandler);
+PROVIDE(DCP_VMI = DefaultHandler);
+PROVIDE(TRNG = DefaultHandler);
+PROVIDE(SAI1 = DefaultHandler);
+PROVIDE(RTWDOG = DefaultHandler);
+PROVIDE(SAI3_RX = DefaultHandler);
+PROVIDE(SAI3_TX = DefaultHandler);
+PROVIDE(SPDIF = DefaultHandler);
+PROVIDE(PMU = DefaultHandler);
+PROVIDE(XBAR1_IRQ_0_1_2_3 = DefaultHandler);
+PROVIDE(TEMP_LOW_HIGH = DefaultHandler);
+PROVIDE(TEMP_PANIC = DefaultHandler);
+PROVIDE(USB_PHY = DefaultHandler);
+PROVIDE(GPC = DefaultHandler);
+PROVIDE(ADC1 = DefaultHandler);
+PROVIDE(FLEXIO1 = DefaultHandler);
+PROVIDE(DCDC = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO1_COMBINED_16_31 = DefaultHandler);
+PROVIDE(GPIO2_COMBINED_0_15 = DefaultHandler);
+PROVIDE(GPIO5_COMBINED_0_15 = DefaultHandler);
+PROVIDE(WDOG1 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ0 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ1 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ2 = DefaultHandler);
+PROVIDE(ADC_ETC_IRQ3 = DefaultHandler);
+PROVIDE(ADC_ETC_ERROR_IRQ = DefaultHandler);
diff --git a/chips/imxrt1010/src/iomuxc.rs b/chips/imxrt1010/src/iomuxc.rs
new file mode 100644
index 0000000..7745808
--- /dev/null
+++ b/chips/imxrt1010/src/iomuxc.rs
@@ -0,0 +1,100 @@
+pub type RegisterBlock = imxrt_drivers_iomuxc_10xx::iomuxc::RegisterBlock<16, 44, 45>;
+
+pub use imxrt_drivers_iomuxc_10xx::iomuxc::{SELECT_INPUT, SW_MUX_CTL_PAD, SW_PAD_CTL_PAD};
+
+/// Indices for `sw_[pad|mux]_ctl_pad` registers.
+pub mod pad {
+ pub const GPIO_AD_14: usize = 0;
+ pub const GPIO_AD_13: usize = 1;
+ pub const GPIO_AD_12: usize = 2;
+ pub const GPIO_AD_11: usize = 3;
+ pub const GPIO_AD_10: usize = 4;
+ pub const GPIO_AD_09: usize = 5;
+ pub const GPIO_AD_08: usize = 6;
+ pub const GPIO_AD_07: usize = 7;
+ pub const GPIO_AD_06: usize = 8;
+ pub const GPIO_AD_05: usize = 9;
+ pub const GPIO_AD_04: usize = 10;
+ pub const GPIO_AD_03: usize = 11;
+ pub const GPIO_AD_02: usize = 12;
+ pub const GPIO_AD_01: usize = 13;
+ pub const GPIO_AD_00: usize = 14;
+ pub const GPIO_SD_14: usize = 15;
+ pub const GPIO_SD_13: usize = 16;
+ pub const GPIO_SD_12: usize = 17;
+ pub const GPIO_SD_11: usize = 18;
+ pub const GPIO_SD_10: usize = 19;
+ pub const GPIO_SD_09: usize = 20;
+ pub const GPIO_SD_08: usize = 21;
+ pub const GPIO_SD_07: usize = 22;
+ pub const GPIO_SD_06: usize = 23;
+ pub const GPIO_SD_05: usize = 24;
+ pub const GPIO_SD_04: usize = 25;
+ pub const GPIO_SD_03: usize = 26;
+ pub const GPIO_SD_02: usize = 27;
+ pub const GPIO_SD_01: usize = 28;
+ pub const GPIO_SD_00: usize = 29;
+ pub const GPIO_13: usize = 30;
+ pub const GPIO_12: usize = 31;
+ pub const GPIO_11: usize = 32;
+ pub const GPIO_10: usize = 33;
+ pub const GPIO_09: usize = 34;
+ pub const GPIO_08: usize = 35;
+ pub const GPIO_07: usize = 36;
+ pub const GPIO_06: usize = 37;
+ pub const GPIO_05: usize = 38;
+ pub const GPIO_04: usize = 39;
+ pub const GPIO_03: usize = 40;
+ pub const GPIO_02: usize = 41;
+ pub const GPIO_01: usize = 42;
+ pub const GPIO_00: usize = 43;
+}
+
+/// Indices for `select_input` registers.
+pub mod select_input {
+ pub const USB_OTG_ID: usize = 0;
+ pub const FLEXPWM1_PWMA_0: usize = 1;
+ pub const FLEXPWM1_PWMA_1: usize = 2;
+ pub const FLEXPWM1_PWMA_2: usize = 3;
+ pub const FLEXPWM1_PWMA_3: usize = 4;
+ pub const FLEXPWM1_PWMB_0: usize = 5;
+ pub const FLEXPWM1_PWMB_1: usize = 6;
+ pub const FLEXPWM1_PWMB_2: usize = 7;
+ pub const FLEXPWM1_PWMB_3: usize = 8;
+ pub const FLEXSPI_DQS_FA: usize = 9;
+ pub const FLEXSPI_DQS_FB: usize = 10;
+ pub const KPP_COL_0: usize = 11;
+ pub const KPP_COL_1: usize = 12;
+ pub const KPP_COL_2: usize = 13;
+ pub const KPP_COL_3: usize = 14;
+ pub const KPP_ROW_0: usize = 15;
+ pub const KPP_ROW_1: usize = 16;
+ pub const KPP_ROW_2: usize = 17;
+ pub const KPP_ROW_3: usize = 18;
+ pub const LPI2C1_HREQ: usize = 19;
+ pub const LPI2C1_SCL: usize = 20;
+ pub const LPI2C1_SDA: usize = 21;
+ pub const LPI2C2_SCL: usize = 22;
+ pub const LPI2C2_SDA: usize = 23;
+ pub const LPSPI1_PCS: usize = 24;
+ pub const LPSPI1_SCK: usize = 25;
+ pub const LPSPI1_SDI: usize = 26;
+ pub const LPSPI1_SDO: usize = 27;
+ pub const LPSPI2_PCS: usize = 28;
+ pub const LPSPI2_SCK: usize = 29;
+ pub const LPSPI2_SDI: usize = 30;
+ pub const LPSPI2_SDO: usize = 31;
+ pub const LPUART1_RXD: usize = 32;
+ pub const LPUART1_TXD: usize = 33;
+ pub const LPUART2_RXD: usize = 34;
+ pub const LPUART2_TXD: usize = 35;
+ pub const LPUART3_RXD: usize = 36;
+ pub const LPUART3_TXD: usize = 37;
+ pub const LPUART4_RXD: usize = 38;
+ pub const LPUART4_TXD: usize = 39;
+ pub const NMI_GLUE_NMI: usize = 40;
+ pub const SPDIF_IN1: usize = 41;
+ pub const SPDIF_TX_CLK2: usize = 42;
+ pub const USB_OTG_OC: usize = 43;
+ pub const XEV_GLUE_RXEV: usize = 44;
+}
diff --git a/chips/imxrt1010/src/lib.rs b/chips/imxrt1010/src/lib.rs
new file mode 100644
index 0000000..1c45430
--- /dev/null
+++ b/chips/imxrt1010/src/lib.rs
@@ -0,0 +1,76 @@
+//! Drivers for iMXRT1010 MCUs.
+
+#![no_std]
+
+pub use ral_registers::{Instance, modify_reg, read_reg, write_reg};
+
+mod rt;
+pub use rt::*;
+
+pub mod iomuxc;
+
+/// Clock control module.
+pub mod ccm {
+ pub use imxrt_drivers_ccm_10xx::ahb::pll6_500mhz::*;
+
+ pub use imxrt_drivers_ccm_10xx::ccm::{
+ CCM, LowPowerMode, ahb_clk, clock_gate, flexspi1_clk_root_pll2 as flexspi1_clk, ipg_clk,
+ low_power_mode, lpi2c_clk, lpspi_clk, perclk_clk, set_low_power_mode, uart_clk,
+ };
+ pub use imxrt_drivers_ccm_10xx::ccm_analog::{CCM_ANALOG, pll2, pll3};
+
+ /// Peripheral clock 2.
+ pub mod periph_clk2 {
+ pub use imxrt_drivers_ccm_10xx::ccm::periph_clk2::{Selection, selection, set_selection};
+ }
+
+ pub use imxrt_drivers_ccm_10xx::ccm::pre_periph_clk_pll6 as pre_periph_clk;
+
+ pub use imxrt_drivers_ccm_10xx::ccm_analog::pll6_500mhz as pll6;
+
+ pub mod gates {
+ use super::clock_gate::Locator::{self, *};
+
+ pub const FLEXSPI: Locator = Ccgr6Cg05;
+ }
+
+ pub use imxrt_drivers_ccm_10xx::ral;
+}
+
+pub use imxrt_drivers_dcdc as dcdc;
+pub use imxrt_drivers_flexspi as flexspi;
+pub use imxrt_drivers_gpio as gpio;
+pub use imxrt_drivers_lpspi as lpspi;
+pub use imxrt_drivers_pit as pit;
+pub use imxrt_drivers_rtwdog as rtwdog;
+
+/// Peripheral instances.
+pub mod instances {
+ ral_registers::instances! {
+ // Safety: The reference manual confirms there are register
+ // blocks at this address matching this shape.
+ unsafe {
+ /// Access CCM registers.
+ pub ccm<imxrt_drivers_ccm_10xx::ral::ccm::RegisterBlock> = 0x400F_C000;
+ /// Access CCM\_ANALOG registers.
+ pub ccm_analog<imxrt_drivers_ccm_10xx::ral::ccm_analog::RegisterBlock> = 0x400D_8000;
+
+ pub dcdc<crate::dcdc::RegisterBlock> = 0x4008_0000;
+
+ pub gpio1<crate::gpio::RegisterBlock> = 0x401b_8000;
+ pub gpio5<crate::gpio::RegisterBlock> = 0x400c_0000;
+ pub gpio2<crate::gpio::RegisterBlock> = 0x4200_0000;
+
+ pub iomuxc<crate::iomuxc::RegisterBlock> = 0x401F_8000;
+
+ pub flexspi<crate::flexspi::RegisterBlock> = 0x400A_0000;
+
+ pub pit<crate::pit::RegisterBlock> = 0x4008_4000;
+
+ pub lpspi1<crate::lpspi::RegisterBlock> = 0x4019_4000;
+ pub lpspi2<crate::lpspi::RegisterBlock> = 0x4019_8000;
+
+ pub wdog3<crate::rtwdog::RegisterBlock> = 0x400B_C000;
+ }
+ }
+}
diff --git a/chips/imxrt1010/src/rt.rs b/chips/imxrt1010/src/rt.rs
new file mode 100644
index 0000000..2fdbec8
--- /dev/null
+++ b/chips/imxrt1010/src/rt.rs
@@ -0,0 +1,361 @@
+#![allow(non_camel_case_types)]
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Interrupt {
+ #[doc = "0 - DMA0"]
+ DMA0 = 0,
+ #[doc = "1 - DMA1"]
+ DMA1 = 1,
+ #[doc = "2 - DMA2"]
+ DMA2 = 2,
+ #[doc = "3 - DMA3"]
+ DMA3 = 3,
+ #[doc = "4 - DMA4"]
+ DMA4 = 4,
+ #[doc = "5 - DMA5"]
+ DMA5 = 5,
+ #[doc = "6 - DMA6"]
+ DMA6 = 6,
+ #[doc = "7 - DMA7"]
+ DMA7 = 7,
+ #[doc = "8 - DMA8"]
+ DMA8 = 8,
+ #[doc = "9 - DMA9"]
+ DMA9 = 9,
+ #[doc = "10 - DMA10"]
+ DMA10 = 10,
+ #[doc = "11 - DMA11"]
+ DMA11 = 11,
+ #[doc = "12 - DMA12"]
+ DMA12 = 12,
+ #[doc = "13 - DMA13"]
+ DMA13 = 13,
+ #[doc = "14 - DMA14"]
+ DMA14 = 14,
+ #[doc = "15 - DMA15"]
+ DMA15 = 15,
+ #[doc = "16 - DMA_ERROR"]
+ DMA_ERROR = 16,
+ #[doc = "20 - LPUART1"]
+ LPUART1 = 20,
+ #[doc = "21 - LPUART2"]
+ LPUART2 = 21,
+ #[doc = "22 - LPUART3"]
+ LPUART3 = 22,
+ #[doc = "23 - LPUART4"]
+ LPUART4 = 23,
+ #[doc = "24 - PIT"]
+ PIT = 24,
+ #[doc = "25 - USB_OTG1"]
+ USB_OTG1 = 25,
+ #[doc = "26 - FLEXSPI"]
+ FLEXSPI = 26,
+ #[doc = "27 - FLEXRAM"]
+ FLEXRAM = 27,
+ #[doc = "28 - LPI2C1"]
+ LPI2C1 = 28,
+ #[doc = "29 - LPI2C2"]
+ LPI2C2 = 29,
+ #[doc = "30 - GPT1"]
+ GPT1 = 30,
+ #[doc = "31 - GPT2"]
+ GPT2 = 31,
+ #[doc = "32 - LPSPI1"]
+ LPSPI1 = 32,
+ #[doc = "33 - LPSPI2"]
+ LPSPI2 = 33,
+ #[doc = "34 - PWM1_0"]
+ PWM1_0 = 34,
+ #[doc = "35 - PWM1_1"]
+ PWM1_1 = 35,
+ #[doc = "36 - PWM1_2"]
+ PWM1_2 = 36,
+ #[doc = "37 - PWM1_3"]
+ PWM1_3 = 37,
+ #[doc = "38 - PWM1_FAULT"]
+ PWM1_FAULT = 38,
+ #[doc = "39 - KPP"]
+ KPP = 39,
+ #[doc = "40 - SRC"]
+ SRC = 40,
+ #[doc = "41 - GPR (aka \"GPC\") interrupt request"]
+ GPR_IRQ = 41,
+ #[doc = "42 - CCM_1"]
+ CCM_1 = 42,
+ #[doc = "43 - CCM_2"]
+ CCM_2 = 43,
+ #[doc = "44 - EWM"]
+ EWM = 44,
+ #[doc = "45 - WDOG2"]
+ WDOG2 = 45,
+ #[doc = "46 - SNVS_HP_WRAPPER"]
+ SNVS_HP_WRAPPER = 46,
+ #[doc = "47 - SNVS_HP_WRAPPER_TZ"]
+ SNVS_HP_WRAPPER_TZ = 47,
+ #[doc = "48 - SNVS_LP_WRAPPER"]
+ SNVS_LP_WRAPPER = 48,
+ #[doc = "49 - CSU"]
+ CSU = 49,
+ #[doc = "50 - DCP"]
+ DCP = 50,
+ #[doc = "51 - DCP_VMI"]
+ DCP_VMI = 51,
+ #[doc = "53 - TRNG"]
+ TRNG = 53,
+ #[doc = "56 - SAI1"]
+ SAI1 = 56,
+ #[doc = "57 - RTWDOG"]
+ RTWDOG = 57,
+ #[doc = "58 - SAI3_RX"]
+ SAI3_RX = 58,
+ #[doc = "59 - SAI3_TX"]
+ SAI3_TX = 59,
+ #[doc = "60 - SPDIF"]
+ SPDIF = 60,
+ #[doc = "61 - PMU"]
+ PMU = 61,
+ #[doc = "62 - XBAR1_IRQ_0_1_2_3"]
+ XBAR1_IRQ_0_1_2_3 = 62,
+ #[doc = "63 - TEMP_LOW_HIGH"]
+ TEMP_LOW_HIGH = 63,
+ #[doc = "64 - TEMP_PANIC"]
+ TEMP_PANIC = 64,
+ #[doc = "65 - USB_PHY"]
+ USB_PHY = 65,
+ #[doc = "66 - GPC"]
+ GPC = 66,
+ #[doc = "67 - ADC1"]
+ ADC1 = 67,
+ #[doc = "68 - FLEXIO1"]
+ FLEXIO1 = 68,
+ #[doc = "69 - DCDC"]
+ DCDC = 69,
+ #[doc = "70 - GPIO1_COMBINED_0_15"]
+ GPIO1_COMBINED_0_15 = 70,
+ #[doc = "71 - GPIO1_COMBINED_16_31"]
+ GPIO1_COMBINED_16_31 = 71,
+ #[doc = "72 - GPIO2_COMBINED_0_15"]
+ GPIO2_COMBINED_0_15 = 72,
+ #[doc = "73 - GPIO5_COMBINED_0_15"]
+ GPIO5_COMBINED_0_15 = 73,
+ #[doc = "74 - WDOG1"]
+ WDOG1 = 74,
+ #[doc = "75 - ADC_ETC_IRQ0"]
+ ADC_ETC_IRQ0 = 75,
+ #[doc = "76 - ADC_ETC_IRQ1"]
+ ADC_ETC_IRQ1 = 76,
+ #[doc = "77 - ADC_ETC_IRQ2"]
+ ADC_ETC_IRQ2 = 77,
+ #[doc = "78 - ADC_ETC_IRQ3"]
+ ADC_ETC_IRQ3 = 78,
+ #[doc = "79 - ADC_ETC_ERROR_IRQ"]
+ ADC_ETC_ERROR_IRQ = 79,
+}
+pub type interrupt = Interrupt;
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+ #[inline(always)]
+ fn number(self) -> u16 {
+ self as u16
+ }
+}
+
+mod _vectors {
+ unsafe extern "C" {
+ fn DMA0();
+ fn DMA1();
+ fn DMA2();
+ fn DMA3();
+ fn DMA4();
+ fn DMA5();
+ fn DMA6();
+ fn DMA7();
+ fn DMA8();
+ fn DMA9();
+ fn DMA10();
+ fn DMA11();
+ fn DMA12();
+ fn DMA13();
+ fn DMA14();
+ fn DMA15();
+ fn DMA_ERROR();
+ fn LPUART1();
+ fn LPUART2();
+ fn LPUART3();
+ fn LPUART4();
+ fn PIT();
+ fn USB_OTG1();
+ fn FLEXSPI();
+ fn FLEXRAM();
+ fn LPI2C1();
+ fn LPI2C2();
+ fn GPT1();
+ fn GPT2();
+ fn LPSPI1();
+ fn LPSPI2();
+ fn PWM1_0();
+ fn PWM1_1();
+ fn PWM1_2();
+ fn PWM1_3();
+ fn PWM1_FAULT();
+ fn KPP();
+ fn SRC();
+ fn GPR_IRQ();
+ fn CCM_1();
+ fn CCM_2();
+ fn EWM();
+ fn WDOG2();
+ fn SNVS_HP_WRAPPER();
+ fn SNVS_HP_WRAPPER_TZ();
+ fn SNVS_LP_WRAPPER();
+ fn CSU();
+ fn DCP();
+ fn DCP_VMI();
+ fn TRNG();
+ fn SAI1();
+ fn RTWDOG();
+ fn SAI3_RX();
+ fn SAI3_TX();
+ fn SPDIF();
+ fn PMU();
+ fn XBAR1_IRQ_0_1_2_3();
+ fn TEMP_LOW_HIGH();
+ fn TEMP_PANIC();
+ fn USB_PHY();
+ fn GPC();
+ fn ADC1();
+ fn FLEXIO1();
+ fn DCDC();
+ fn GPIO1_COMBINED_0_15();
+ fn GPIO1_COMBINED_16_31();
+ fn GPIO2_COMBINED_0_15();
+ fn GPIO5_COMBINED_0_15();
+ fn WDOG1();
+ fn ADC_ETC_IRQ0();
+ fn ADC_ETC_IRQ1();
+ fn ADC_ETC_IRQ2();
+ fn ADC_ETC_IRQ3();
+ fn ADC_ETC_ERROR_IRQ();
+ }
+ pub union Vector {
+ _handler: unsafe extern "C" fn(),
+ _reserved: u32,
+ }
+ #[cfg_attr(target_os = "none", unsafe(link_section = ".vector_table.interrupts"))]
+ #[unsafe(no_mangle)]
+ pub static __INTERRUPTS: [Vector; 80] = [
+ Vector { _handler: DMA0 },
+ Vector { _handler: DMA1 },
+ Vector { _handler: DMA2 },
+ Vector { _handler: DMA3 },
+ Vector { _handler: DMA4 },
+ Vector { _handler: DMA5 },
+ Vector { _handler: DMA6 },
+ Vector { _handler: DMA7 },
+ Vector { _handler: DMA8 },
+ Vector { _handler: DMA9 },
+ Vector { _handler: DMA10 },
+ Vector { _handler: DMA11 },
+ Vector { _handler: DMA12 },
+ Vector { _handler: DMA13 },
+ Vector { _handler: DMA14 },
+ Vector { _handler: DMA15 },
+ Vector {
+ _handler: DMA_ERROR,
+ },
+ Vector { _reserved: 0 },
+ Vector { _reserved: 0 },
+ Vector { _reserved: 0 },
+ Vector { _handler: LPUART1 },
+ Vector { _handler: LPUART2 },
+ Vector { _handler: LPUART3 },
+ Vector { _handler: LPUART4 },
+ Vector { _handler: PIT },
+ Vector { _handler: USB_OTG1 },
+ Vector { _handler: FLEXSPI },
+ Vector { _handler: FLEXRAM },
+ Vector { _handler: LPI2C1 },
+ Vector { _handler: LPI2C2 },
+ Vector { _handler: GPT1 },
+ Vector { _handler: GPT2 },
+ Vector { _handler: LPSPI1 },
+ Vector { _handler: LPSPI2 },
+ Vector { _handler: PWM1_0 },
+ Vector { _handler: PWM1_1 },
+ Vector { _handler: PWM1_2 },
+ Vector { _handler: PWM1_3 },
+ Vector {
+ _handler: PWM1_FAULT,
+ },
+ Vector { _handler: KPP },
+ Vector { _handler: SRC },
+ Vector { _handler: GPR_IRQ },
+ Vector { _handler: CCM_1 },
+ Vector { _handler: CCM_2 },
+ Vector { _handler: EWM },
+ Vector { _handler: WDOG2 },
+ Vector {
+ _handler: SNVS_HP_WRAPPER,
+ },
+ Vector {
+ _handler: SNVS_HP_WRAPPER_TZ,
+ },
+ Vector {
+ _handler: SNVS_LP_WRAPPER,
+ },
+ Vector { _handler: CSU },
+ Vector { _handler: DCP },
+ Vector { _handler: DCP_VMI },
+ Vector { _reserved: 0 },
+ Vector { _handler: TRNG },
+ Vector { _reserved: 0 },
+ Vector { _reserved: 0 },
+ Vector { _handler: SAI1 },
+ Vector { _handler: RTWDOG },
+ Vector { _handler: SAI3_RX },
+ Vector { _handler: SAI3_TX },
+ Vector { _handler: SPDIF },
+ Vector { _handler: PMU },
+ Vector {
+ _handler: XBAR1_IRQ_0_1_2_3,
+ },
+ Vector {
+ _handler: TEMP_LOW_HIGH,
+ },
+ Vector {
+ _handler: TEMP_PANIC,
+ },
+ Vector { _handler: USB_PHY },
+ Vector { _handler: GPC },
+ Vector { _handler: ADC1 },
+ Vector { _handler: FLEXIO1 },
+ Vector { _handler: DCDC },
+ Vector {
+ _handler: GPIO1_COMBINED_0_15,
+ },
+ Vector {
+ _handler: GPIO1_COMBINED_16_31,
+ },
+ Vector {
+ _handler: GPIO2_COMBINED_0_15,
+ },
+ Vector {
+ _handler: GPIO5_COMBINED_0_15,
+ },
+ Vector { _handler: WDOG1 },
+ Vector {
+ _handler: ADC_ETC_IRQ0,
+ },
+ Vector {
+ _handler: ADC_ETC_IRQ1,
+ },
+ Vector {
+ _handler: ADC_ETC_IRQ2,
+ },
+ Vector {
+ _handler: ADC_ETC_IRQ3,
+ },
+ Vector {
+ _handler: ADC_ETC_ERROR_IRQ,
+ },
+ ];
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-26 16:54:57 +0000