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| author | awygle <awygle@gmail.com> | 2020-11-04 22:52:12 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-11-05 06:52:12 +0000 |
| commit | ec65568d91dca4ca2ff7da22b90ad6574bbad68a (patch) | |
| tree | b99cf827aaf1edcfb34f3aae5228d3e81c0d916e /nmigen_boards/genesys2.py | |
| parent | bcc14672994a3cdd04b7c0e1620d6f5e05145d94 (diff) | |
Factor out I2C resource.
Diffstat (limited to 'nmigen_boards/genesys2.py')
| -rw-r--r-- | nmigen_boards/genesys2.py | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py index 40dbced..1c4ee54 100644 --- a/nmigen_boards/genesys2.py +++ b/nmigen_boards/genesys2.py @@ -52,10 +52,8 @@ class Genesys2Platform(Xilinx7SeriesPlatform): Attrs(IOSTANDARD="LVCMOS33")), UARTResource(0, rx="Y20", tx="Y23", attrs=Attrs(IOSTANDARD="LVCMOS33")), - Resource("i2c", 0, - Subsignal("scl", Pins("AE30", dir="io")), - Subsignal("sda", Pins("AF30", dir="io")), - Attrs(IOSTANDARD="LVCMOS33")), + I2CResource(0, scl="AE30", sda="AF30", + attrs=Attrs(IOSTANDARD="LVCMOS33")), Resource("ddr3", 0, Subsignal("rst", PinsN("AG5", dir="o"), Attrs(IOSTANDARD="SSTL15")), |