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path: root/nmigen_boards/nexys4ddr.py
AgeCommit message (Expand)Author
2021-12-10Rename nMigen to Amaranth HDL.whitequark
2021-08-13nexys3ddr: Fix I/O voltage for SW8 and SW9Jonathan Neuschäfer
2021-06-03[breaking-change] Factor out PS2Resource.S.J.R. van Schaik
2021-05-31[breaking-change] Factor out VGAResource.S.J.R. van Schaik
2020-11-26[breaking-change] Add `_n` suffix to argument names of pins with fixed invert...GuzTech
2020-07-16[breaking-change] Update SPI pin names.ECP5-PCIe
2020-06-11[breaking-change] nexys4ddr: fix UART RTS/CTS pins.Ivan Grokhotkov
2020-03-17nexys4ddr: enable pushbutton reset.Stuart Olsen
2020-01-15Add Digilent Nexys 4 DDR board.Nicolas Robin