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2020-11-24Add DE1-SoC support.H-S-S-11
2020-11-13Add Quickfeather.Jan Kowalewski
Co-authored-by: whitequark <whitequark@whitequark.org> Co-Authored-By: Kamil Rakoczy <krakoczy@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2020-11-13Use importlib_metadata instead of pkg_resources.whitequark
2020-11-05Factor out I2C resource.awygle
2020-10-15arty_s7: add openocd and flashing support.William D. Jones
2020-10-09genesys2: convert `ulpi` to ULPIResourceKatherine Temkin
2020-10-09genesys2: correctly specify I/O attributes for VADJ banksKatherine Temkin
2020-09-21ulx3s: fix copy-paste error in GPIO mappings.Thomas Daede
2020-09-13ulx3s: correct speed grade.Thomas Daede
The boards available on the crowdsupply page, as well as my hand-built board, all seem to use speed grade 6.
2020-09-06resources.memory: make cs pin optional for SDRAMResourcemarble
2020-08-26arty_z7: fix PMOD 1 (JB) pinout.DaKnig
2020-08-25arty_a7: fix `rst` pin polarity.Mariusz Glebocki
2020-08-17Added Arty S7 supportStaf Verhaegen
This is based on Arty A7 file. Some things are handled differently: * Rename cpu_reset resource to rst and use it as default circuit reset. * Use Vivado for programming the board. * Don't overload .bin generation; it does not seem to make a difference. * Generate also mcs file. This is used by openFPGALoader for programming into SPI Flash. Arty S7-50 has been tested on the board by blinky test; Arty S7-25 only bitstream generation, not on the board.
2020-08-15Use correct IO attribute for ECP5 FPGAsOguz Meteer
This changes several incorrect IO_STANDARD attributes to IO_TYPE. Signed-off-by: Oguz Meteer <info@guztech.nl>
2020-08-10[breaking-change] Arty A7: rename cpu_reset resource to rst. (#102)Staf Verhaegen
It's now define properly as input and used as default reset.
2020-08-07versa_ecp5: Fix DDR3 IO types, using the types from Lattice's DDR3 demo lpfJean THOMAS
2020-08-06resources: allow use of ULPI PHYs with active-low RST pinsKatherine Temkin
Also, fixes a typo that affected PHYs with rst specified
2020-08-06Add Hackaday Supercon19Badge.Katherine Temkin
2020-08-05Add MicroZed Z010 and Z020.Robin Heinemann
2020-08-03ecpix5: add termination attributes to DDR3 signalsJean THOMAS
2020-07-28Add iCEBreaker Bitsy.Kate Temkin
2020-07-27Add ULX3S.Kate Temkin
2020-07-27orangecrab_r0_2: fix sense diffpair.Joshua Koike
2020-07-27orangecrab_r0_2: convert sense to diffpairJoshua Koike
2020-07-22tinyfpga_axN: use vendor.lattice_machxo2, not .lattice_machxo_2_3l.whitequark
This restores compatibility with nMigen 0.2.
2020-07-21fomu_pvt: fix typoRobin Ole Heinemann
2020-07-19Factor out direct USB and ULPI resources.Kate Temkin
2020-07-18mercury: fix SPI rolesRobin Ole Heinemann
2020-07-16ecpix5: fix PMOD4 pins.Jean-François Nguyen
2020-07-16[breaking-change] Update SPI pin names.ECP5-PCIe
The new names follow the OSHWA convention described at: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
2020-07-15Add OrangeCrab r0.1Mike Walters
2020-07-14orangecrab_r0_2: fix dq pin definitions.Mike Walters
2020-07-13orangecrab_r0_2: IO_STANDARD -> IO_TYPEGwenhael Goavec-Merou
2020-07-13Add OrangeCrab R2.0 board.Thomas Daede
2020-07-13Add RGB LEDs to blinky test.Thomas Daede
2020-07-09Add ECPIX-5 support.Jean-François Nguyen
2020-07-08kcu105: merge temperature grade into speed grade.whitequark
2020-07-04de0_cv: fix ba and cs pins of the SDRAM resource.Andrew Clark
2020-07-02[breaking-change] resources.memory: add missing inversion on SRAMResource(dm=).whitequark
The semantics should be that a high bit of data mask (UB#LB#) enables the write to the corresponding byte.
2020-06-28ecp5_evn: add SPI Flash, UART, and EXTCLK peripheralsAled Cuda
2020-06-27de0_cv: remove SD card WP pin (not present on this board).whitequark
2020-06-22resources: allow UARTResource without control signals to have no role.whitequark
2020-06-22{machXO3_sk→machxo3_sk}: follow naming conventionswhitequark
2020-06-22machXO3_sk: fix platform nameGwenhael Goavec-Merou
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2020-06-21Add Lattice MachXO3LF Starter KitGwenhael Goavec-Merou
2020-06-21tinyfpga_axN: use lattice_machxo_2_3l instead of lattice_machxo2Gwenhael Goavec-Merou
2020-06-11icestick: fix UART flow control pins.Ivan Grokhotkov
UART flow control pins match the signal names in the schematic, but directions are reversed. Fix by setting role=dce.
2020-06-11[breaking-change] ice40_hx8k_b_evn: fix UART flow control pins.Ivan Grokhotkov
RTS/CTS and DTR/DSR pairs have been swapped to work around the signal direction in UARTResource. Un-reverse the signals, making the names match the schematic. Fix the direction by setting role=dce. Ref. http://www.latticesemi.com/view_document?document_id=50373
2020-06-11de0: fix UART RTS/CTS direction.Ivan Grokhotkov
RTS and CTS match the schematic, but the direction is incorrect: CTS is output, RTS is input. Fix by setting role=dce. Ref. https://www.intel.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-5804152209-de0-user-manual.pdf
2020-06-11[breaking-change] nexys4ddr: fix UART RTS/CTS pins.Ivan Grokhotkov
According to the schematic, RTS is E5 and CTS is D3. Previously these were reversed to work around signal direction set in UARTResource. Un-reverse the signals, and set correct direction by passing role=dce. Ref. https://reference.digilentinc.com/_media/nexys4-ddr:nexys_4_ddr_sch.pdf
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